// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.2 (win64) Build 3671981 Fri Oct 14 05:00:03 MDT 2022
// Date        : Wed Sep  4 09:41:22 2024
// Host        : DESKTOP-MTCIU5H running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               h:/USL2C128/fpga/local/afe580x_rx64_ku060_pciex8_xdma/ip/axi4_dwtrans/axi4_dwtrans_sim_netlist.v
// Design      : axi4_dwtrans
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xcku060-ffva1156-2-i
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "axi4_dwtrans,axi_dwidth_converter_v2_1_27_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_dwidth_converter_v2_1_27_top,Vivado 2022.2" *) 
(* NotValidForBitStream *)
module axi4_dwtrans
   (s_axi_aclk,
    s_axi_aresetn,
    s_axi_awid,
    s_axi_awaddr,
    s_axi_awlen,
    s_axi_awsize,
    s_axi_awburst,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos,
    s_axi_awvalid,
    s_axi_awready,
    s_axi_wdata,
    s_axi_wstrb,
    s_axi_wlast,
    s_axi_wvalid,
    s_axi_wready,
    s_axi_bid,
    s_axi_bresp,
    s_axi_bvalid,
    s_axi_bready,
    s_axi_arid,
    s_axi_araddr,
    s_axi_arlen,
    s_axi_arsize,
    s_axi_arburst,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos,
    s_axi_arvalid,
    s_axi_arready,
    s_axi_rid,
    s_axi_rdata,
    s_axi_rresp,
    s_axi_rlast,
    s_axi_rvalid,
    s_axi_rready,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    m_axi_awvalid,
    m_axi_awready,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wvalid,
    m_axi_wready,
    m_axi_bresp,
    m_axi_bvalid,
    m_axi_bready,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    m_axi_arvalid,
    m_axi_arready,
    m_axi_rdata,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_rvalid,
    m_axi_rready);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input s_axi_aclk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [3:0]s_axi_awid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [63:0]s_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [255:0]s_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [31:0]s_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [3:0]s_axi_bid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [3:0]s_axi_arid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [63:0]s_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [3:0]s_axi_rid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [255:0]s_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 256, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 4, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [63:0]m_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [127:0]m_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [15:0]m_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [63:0]m_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [127:0]m_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 64, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;

  wire [63:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  wire [7:0]m_axi_arlen;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire [3:0]m_axi_arregion;
  wire [2:0]m_axi_arsize;
  wire m_axi_arvalid;
  wire [63:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [7:0]m_axi_awlen;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire [2:0]m_axi_awsize;
  wire m_axi_awvalid;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [127:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire [1:0]m_axi_rresp;
  wire m_axi_rvalid;
  wire [127:0]m_axi_wdata;
  wire m_axi_wlast;
  wire m_axi_wready;
  wire [15:0]m_axi_wstrb;
  wire m_axi_wvalid;
  wire s_axi_aclk;
  wire [63:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire s_axi_aresetn;
  wire [3:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire s_axi_arready;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [63:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [3:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire s_axi_awready;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [3:0]s_axi_bid;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire [255:0]s_axi_rdata;
  wire [3:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire s_axi_rvalid;
  wire [255:0]s_axi_wdata;
  wire s_axi_wready;
  wire [31:0]s_axi_wstrb;
  wire s_axi_wvalid;

  (* C_AXI_ADDR_WIDTH = "64" *) 
  (* C_AXI_IS_ACLK_ASYNC = "0" *) 
  (* C_AXI_PROTOCOL = "0" *) 
  (* C_AXI_SUPPORTS_READ = "1" *) 
  (* C_AXI_SUPPORTS_WRITE = "1" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_FIFO_MODE = "0" *) 
  (* C_MAX_SPLIT_BEATS = "256" *) 
  (* C_M_AXI_ACLK_RATIO = "2" *) 
  (* C_M_AXI_BYTES_LOG = "4" *) 
  (* C_M_AXI_DATA_WIDTH = "128" *) 
  (* C_PACKING_LEVEL = "1" *) 
  (* C_RATIO = "2" *) 
  (* C_RATIO_LOG = "1" *) 
  (* C_SUPPORTS_ID = "1" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_S_AXI_ACLK_RATIO = "1" *) 
  (* C_S_AXI_BYTES_LOG = "5" *) 
  (* C_S_AXI_DATA_WIDTH = "256" *) 
  (* C_S_AXI_ID_WIDTH = "4" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* P_AXI3 = "1" *) 
  (* P_AXI4 = "0" *) 
  (* P_AXILITE = "2" *) 
  (* P_CONVERSION = "2" *) 
  (* P_MAX_SPLIT_BEATS = "256" *) 
  axi4_dwtrans_axi_dwidth_converter_v2_1_27_top inst
       (.m_axi_aclk(1'b0),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_aresetn(1'b0),
        .m_axi_arlen(m_axi_arlen),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arqos(m_axi_arqos),
        .m_axi_arready(m_axi_arready),
        .m_axi_arregion(m_axi_arregion),
        .m_axi_arsize(m_axi_arsize),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awlen(m_axi_awlen),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awqos(m_axi_awqos),
        .m_axi_awready(m_axi_awready),
        .m_axi_awregion(m_axi_awregion),
        .m_axi_awsize(m_axi_awsize),
        .m_axi_awvalid(m_axi_awvalid),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wlast(m_axi_wlast),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wvalid(m_axi_wvalid),
        .s_axi_aclk(s_axi_aclk),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_aresetn(s_axi_aresetn),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arready(s_axi_arready),
        .s_axi_arregion(s_axi_arregion),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awready(s_axi_awready),
        .s_axi_awregion(s_axi_awregion),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bid(s_axi_bid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_bvalid(s_axi_bvalid),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rresp(s_axi_rresp),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wlast(1'b0),
        .s_axi_wready(s_axi_wready),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wvalid(s_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_26_axic_fifo" *) 
module axi4_dwtrans_axi_data_fifo_v2_1_26_axic_fifo
   (dout,
    full,
    empty,
    SR,
    din,
    access_is_incr_q_reg,
    access_is_fix_q_reg,
    \pushed_commands_reg[7] ,
    CLK,
    wr_en,
    \USE_WRITE.wr_cmd_b_ready ,
    out,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    fix_need_to_split_q,
    access_is_incr_q,
    access_is_wrap_q,
    split_ongoing,
    Q,
    \gpr1.dout_i_reg[1] ,
    access_is_fix_q,
    \gpr1.dout_i_reg[1]_0 );
  output [4:0]dout;
  output full;
  output empty;
  output [0:0]SR;
  output [0:0]din;
  output access_is_incr_q_reg;
  output access_is_fix_q_reg;
  output \pushed_commands_reg[7] ;
  input CLK;
  input wr_en;
  input \USE_WRITE.wr_cmd_b_ready ;
  input out;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input fix_need_to_split_q;
  input access_is_incr_q;
  input access_is_wrap_q;
  input split_ongoing;
  input [7:0]Q;
  input [2:0]\gpr1.dout_i_reg[1] ;
  input access_is_fix_q;
  input [3:0]\gpr1.dout_i_reg[1]_0 ;

  wire CLK;
  wire [7:0]Q;
  wire [0:0]SR;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire access_is_fix_q;
  wire access_is_fix_q_reg;
  wire access_is_incr_q;
  wire access_is_incr_q_reg;
  wire access_is_wrap_q;
  wire [0:0]din;
  wire [4:0]dout;
  wire empty;
  wire fix_need_to_split_q;
  wire full;
  wire [2:0]\gpr1.dout_i_reg[1] ;
  wire [3:0]\gpr1.dout_i_reg[1]_0 ;
  wire incr_need_to_split_q;
  wire out;
  wire \pushed_commands_reg[7] ;
  wire split_ongoing;
  wire wr_en;
  wire wrap_need_to_split_q;

  axi4_dwtrans_axi_data_fifo_v2_1_26_fifo_gen inst
       (.CLK(CLK),
        .Q(Q),
        .SR(SR),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_is_fix_q(access_is_fix_q),
        .access_is_fix_q_reg(access_is_fix_q_reg),
        .access_is_incr_q(access_is_incr_q),
        .access_is_incr_q_reg(access_is_incr_q_reg),
        .access_is_wrap_q(access_is_wrap_q),
        .din(din),
        .dout(dout),
        .empty(empty),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(full),
        .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ),
        .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .out(out),
        .\pushed_commands_reg[7] (\pushed_commands_reg[7] ),
        .split_ongoing(split_ongoing),
        .wr_en(wr_en),
        .wrap_need_to_split_q(wrap_need_to_split_q));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_26_axic_fifo" *) 
module axi4_dwtrans_axi_data_fifo_v2_1_26_axic_fifo__parameterized0
   (dout,
    din,
    cmd_push,
    D,
    s_axi_arvalid_0,
    m_axi_arready_0,
    command_ongoing_reg,
    m_axi_arready_1,
    empty_fwft_i_reg,
    empty_fwft_i_reg_0,
    empty_fwft_i_reg_1,
    s_axi_rdata,
    m_axi_arready_2,
    m_axi_rvalid_0,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    s_axi_aresetn,
    \goreg_dm.dout_i_reg[18] ,
    \goreg_dm.dout_i_reg[2] ,
    s_axi_rvalid,
    m_axi_rready,
    p_0_in,
    s_axi_rlast,
    cmd_empty_reg,
    CLK,
    SR,
    access_fit_mi_side_q,
    \gpr1.dout_i_reg[15] ,
    Q,
    fix_need_to_split_q,
    \m_axi_arlen[7]_INST_0_i_1 ,
    access_is_wrap_q,
    split_ongoing,
    s_axi_arvalid,
    E,
    areset_d,
    command_ongoing,
    m_axi_arready,
    out,
    cmd_push_block,
    s_axi_rready,
    m_axi_rvalid,
    p_1_in,
    m_axi_rdata,
    \cmd_depth_reg[5] ,
    cmd_empty,
    s_axi_rid,
    m_axi_arvalid,
    access_is_fix_q,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    \m_axi_arlen[7] ,
    \m_axi_arlen[7]_0 ,
    \m_axi_arlen[7]_INST_0_i_1_0 ,
    \m_axi_arlen[2] ,
    access_is_incr_q,
    \m_axi_arlen[7]_INST_0_i_8 ,
    \m_axi_arlen[7]_INST_0_i_13 ,
    \gpr1.dout_i_reg[29] ,
    si_full_size_q,
    \gpr1.dout_i_reg[15]_0 ,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \gpr1.dout_i_reg[15]_4 ,
    \gpr1.dout_i_reg[15]_5 ,
    \m_axi_arlen[2]_INST_0_i_3 ,
    legal_wrap_len_q,
    first_mi_word,
    s_axi_rvalid_0,
    s_axi_rvalid_1,
    \current_word_1_reg[3] ,
    s_axi_rdata_0_sp_1,
    \current_word_1_reg[4] ,
    \current_word_1_reg[3]_0 ,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[2] ,
    m_axi_rlast,
    cmd_empty_reg_0);
  output [20:0]dout;
  output [11:0]din;
  output cmd_push;
  output [4:0]D;
  output s_axi_arvalid_0;
  output m_axi_arready_0;
  output command_ongoing_reg;
  output m_axi_arready_1;
  output [0:0]empty_fwft_i_reg;
  output [0:0]empty_fwft_i_reg_0;
  output [0:0]empty_fwft_i_reg_1;
  output [255:0]s_axi_rdata;
  output [0:0]m_axi_arready_2;
  output [0:0]m_axi_rvalid_0;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output [0:0]s_axi_aresetn;
  output \goreg_dm.dout_i_reg[18] ;
  output \goreg_dm.dout_i_reg[2] ;
  output s_axi_rvalid;
  output m_axi_rready;
  output [3:0]p_0_in;
  output s_axi_rlast;
  output cmd_empty_reg;
  input CLK;
  input [0:0]SR;
  input access_fit_mi_side_q;
  input [7:0]\gpr1.dout_i_reg[15] ;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1 ;
  input access_is_wrap_q;
  input split_ongoing;
  input s_axi_arvalid;
  input [0:0]E;
  input [1:0]areset_d;
  input command_ongoing;
  input m_axi_arready;
  input out;
  input cmd_push_block;
  input s_axi_rready;
  input m_axi_rvalid;
  input [255:0]p_1_in;
  input [127:0]m_axi_rdata;
  input \cmd_depth_reg[5] ;
  input cmd_empty;
  input [3:0]s_axi_rid;
  input [3:0]m_axi_arvalid;
  input access_is_fix_q;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input [7:0]\m_axi_arlen[7] ;
  input [7:0]\m_axi_arlen[7]_0 ;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  input [2:0]\m_axi_arlen[2] ;
  input access_is_incr_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_8 ;
  input [2:0]\m_axi_arlen[7]_INST_0_i_13 ;
  input \gpr1.dout_i_reg[29] ;
  input si_full_size_q;
  input [0:0]\gpr1.dout_i_reg[15]_0 ;
  input [4:0]\gpr1.dout_i_reg[15]_1 ;
  input \gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input \gpr1.dout_i_reg[15]_4 ;
  input \gpr1.dout_i_reg[15]_5 ;
  input [2:0]\m_axi_arlen[2]_INST_0_i_3 ;
  input legal_wrap_len_q;
  input first_mi_word;
  input [0:0]s_axi_rvalid_0;
  input s_axi_rvalid_1;
  input \current_word_1_reg[3] ;
  input s_axi_rdata_0_sp_1;
  input \current_word_1_reg[4] ;
  input \current_word_1_reg[3]_0 ;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1_reg[2] ;
  input m_axi_rlast;
  input cmd_empty_reg_0;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire access_fit_mi_side_q;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire [1:0]areset_d;
  wire \cmd_depth_reg[5] ;
  wire cmd_empty;
  wire cmd_empty_reg;
  wire cmd_empty_reg_0;
  wire cmd_push;
  wire cmd_push_block;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire \current_word_1_reg[3] ;
  wire \current_word_1_reg[3]_0 ;
  wire \current_word_1_reg[4] ;
  wire [11:0]din;
  wire [20:0]dout;
  wire [0:0]empty_fwft_i_reg;
  wire [0:0]empty_fwft_i_reg_0;
  wire [0:0]empty_fwft_i_reg_1;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire \goreg_dm.dout_i_reg[18] ;
  wire \goreg_dm.dout_i_reg[2] ;
  wire [7:0]\gpr1.dout_i_reg[15] ;
  wire [0:0]\gpr1.dout_i_reg[15]_0 ;
  wire [4:0]\gpr1.dout_i_reg[15]_1 ;
  wire \gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire \gpr1.dout_i_reg[15]_4 ;
  wire \gpr1.dout_i_reg[15]_5 ;
  wire \gpr1.dout_i_reg[29] ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire [2:0]\m_axi_arlen[2] ;
  wire [2:0]\m_axi_arlen[2]_INST_0_i_3 ;
  wire [7:0]\m_axi_arlen[7] ;
  wire [7:0]\m_axi_arlen[7]_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1 ;
  wire [2:0]\m_axi_arlen[7]_INST_0_i_13 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_8 ;
  wire m_axi_arready;
  wire m_axi_arready_0;
  wire m_axi_arready_1;
  wire [0:0]m_axi_arready_2;
  wire [3:0]m_axi_arvalid;
  wire [127:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire m_axi_rvalid;
  wire [0:0]m_axi_rvalid_0;
  wire out;
  wire [3:0]p_0_in;
  wire [255:0]p_1_in;
  wire [0:0]s_axi_aresetn;
  wire s_axi_arvalid;
  wire s_axi_arvalid_0;
  wire [255:0]s_axi_rdata;
  wire s_axi_rdata_0_sn_1;
  wire [3:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire s_axi_rvalid;
  wire [0:0]s_axi_rvalid_0;
  wire s_axi_rvalid_1;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wrap_need_to_split_q;

  assign s_axi_rdata_0_sn_1 = s_axi_rdata_0_sp_1;
  axi4_dwtrans_axi_data_fifo_v2_1_26_fifo_gen__parameterized0 inst
       (.CLK(CLK),
        .D(D),
        .E(E),
        .Q(Q),
        .SR(SR),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(access_is_wrap_q_reg),
        .areset_d(areset_d),
        .\cmd_depth_reg[5] (\cmd_depth_reg[5] ),
        .cmd_empty(cmd_empty),
        .cmd_empty_reg(cmd_empty_reg),
        .cmd_empty_reg_0(cmd_empty_reg_0),
        .cmd_push_block(cmd_push_block),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[2] (\current_word_1_reg[2] ),
        .\current_word_1_reg[3] (\current_word_1_reg[3] ),
        .\current_word_1_reg[3]_0 (\current_word_1_reg[3]_0 ),
        .\current_word_1_reg[4] (\current_word_1_reg[4] ),
        .din(din),
        .dout(dout),
        .empty_fwft_i_reg(empty_fwft_i_reg),
        .empty_fwft_i_reg_0(empty_fwft_i_reg_0),
        .empty_fwft_i_reg_1(empty_fwft_i_reg_1),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .\goreg_dm.dout_i_reg[18] (\goreg_dm.dout_i_reg[18] ),
        .\goreg_dm.dout_i_reg[2] (\goreg_dm.dout_i_reg[2] ),
        .\gpr1.dout_i_reg[15] (\gpr1.dout_i_reg[15]_0 ),
        .\gpr1.dout_i_reg[15]_0 (\gpr1.dout_i_reg[15]_1 ),
        .\gpr1.dout_i_reg[15]_1 (\gpr1.dout_i_reg[15]_2 ),
        .\gpr1.dout_i_reg[15]_2 (\gpr1.dout_i_reg[15]_3 ),
        .\gpr1.dout_i_reg[15]_3 (\gpr1.dout_i_reg[15]_4 ),
        .\gpr1.dout_i_reg[15]_4 (\gpr1.dout_i_reg[15]_5 ),
        .\gpr1.dout_i_reg[29] (\gpr1.dout_i_reg[29] ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_arlen[2] (\m_axi_arlen[2] ),
        .\m_axi_arlen[2]_INST_0_i_3_0 (\m_axi_arlen[2]_INST_0_i_3 ),
        .\m_axi_arlen[7] (\m_axi_arlen[7] ),
        .\m_axi_arlen[7]_0 (\m_axi_arlen[7]_0 ),
        .\m_axi_arlen[7]_INST_0_i_13_0 (\m_axi_arlen[7]_INST_0_i_13 ),
        .\m_axi_arlen[7]_INST_0_i_1_0 (\m_axi_arlen[7]_INST_0_i_1 ),
        .\m_axi_arlen[7]_INST_0_i_1_1 (\m_axi_arlen[7]_INST_0_i_1_0 ),
        .\m_axi_arlen[7]_INST_0_i_8_0 (\m_axi_arlen[7]_INST_0_i_8 ),
        .m_axi_arready(m_axi_arready),
        .m_axi_arready_0(m_axi_arready_0),
        .m_axi_arready_1(m_axi_arready_1),
        .m_axi_arready_2(m_axi_arready_2),
        .\m_axi_arsize[0] ({access_fit_mi_side_q,\gpr1.dout_i_reg[15] }),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_rvalid_0(m_axi_rvalid_0),
        .out(out),
        .p_0_in(p_0_in),
        .p_1_in(p_1_in),
        .s_axi_aresetn(s_axi_aresetn),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_arvalid_0(s_axi_arvalid_0),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rdata_0_sp_1(s_axi_rdata_0_sn_1),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_rvalid_0(s_axi_rvalid_0),
        .s_axi_rvalid_1(s_axi_rvalid_1),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(split_ongoing_reg),
        .wr_en(cmd_push),
        .wrap_need_to_split_q(wrap_need_to_split_q));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_26_axic_fifo" *) 
module axi4_dwtrans_axi_data_fifo_v2_1_26_axic_fifo__parameterized0__xdcDup__1
   (dout,
    \S_AXI_ASIZE_Q_reg[2] ,
    E,
    D,
    s_axi_awvalid_0,
    command_ongoing_reg,
    cmd_b_push_block_reg,
    cmd_b_push_block_reg_0,
    cmd_b_push_block_reg_1,
    cmd_push_block_reg,
    m_axi_awready_0,
    wr_en,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    m_axi_wvalid,
    s_axi_wready,
    s_axi_wvalid_0,
    \goreg_dm.dout_i_reg[18] ,
    \areset_d_reg[0] ,
    CLK,
    SR,
    din,
    Q,
    fix_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_6 ,
    access_is_wrap_q,
    split_ongoing,
    first_mi_word,
    \current_word_1_reg[3] ,
    s_axi_awvalid,
    S_AXI_AREADY_I_reg,
    S_AXI_AREADY_I_reg_0,
    S_AXI_AREADY_I_reg_1,
    command_ongoing,
    m_axi_awready,
    command_ongoing_reg_0,
    cmd_b_push_block,
    out,
    \USE_WRITE.wr_cmd_b_ready ,
    \USE_B_CHANNEL.cmd_b_empty_i_reg ,
    cmd_b_empty,
    cmd_push_block,
    full,
    m_axi_awvalid_INST_0_i_1,
    s_axi_bid,
    access_is_fix_q,
    \m_axi_awlen[7] ,
    \m_axi_awlen[7]_0 ,
    \m_axi_awlen[7]_INST_0_i_6_0 ,
    wrap_need_to_split_q,
    \m_axi_awlen[2] ,
    incr_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_5 ,
    access_is_incr_q,
    \m_axi_awlen[7]_INST_0_i_5_0 ,
    \gpr1.dout_i_reg[29] ,
    si_full_size_q,
    \gpr1.dout_i_reg[15] ,
    \gpr1.dout_i_reg[15]_0 ,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \gpr1.dout_i_reg[15]_4 ,
    \m_axi_awlen[2]_INST_0_i_3 ,
    legal_wrap_len_q,
    s_axi_wvalid,
    m_axi_wready,
    s_axi_wready_0,
    \current_word_1_reg[4] ,
    \current_word_1_reg[4]_0 ,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1[4]_i_2 );
  output [18:0]dout;
  output [10:0]\S_AXI_ASIZE_Q_reg[2] ;
  output [0:0]E;
  output [4:0]D;
  output s_axi_awvalid_0;
  output command_ongoing_reg;
  output cmd_b_push_block_reg;
  output [0:0]cmd_b_push_block_reg_0;
  output cmd_b_push_block_reg_1;
  output cmd_push_block_reg;
  output [0:0]m_axi_awready_0;
  output wr_en;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]s_axi_wvalid_0;
  output [4:0]\goreg_dm.dout_i_reg[18] ;
  output \areset_d_reg[0] ;
  input CLK;
  input [0:0]SR;
  input [9:0]din;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6 ;
  input access_is_wrap_q;
  input split_ongoing;
  input first_mi_word;
  input [1:0]\current_word_1_reg[3] ;
  input s_axi_awvalid;
  input [0:0]S_AXI_AREADY_I_reg;
  input S_AXI_AREADY_I_reg_0;
  input S_AXI_AREADY_I_reg_1;
  input command_ongoing;
  input m_axi_awready;
  input command_ongoing_reg_0;
  input cmd_b_push_block;
  input out;
  input \USE_WRITE.wr_cmd_b_ready ;
  input \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  input cmd_b_empty;
  input cmd_push_block;
  input full;
  input [3:0]m_axi_awvalid_INST_0_i_1;
  input [3:0]s_axi_bid;
  input access_is_fix_q;
  input [7:0]\m_axi_awlen[7] ;
  input [7:0]\m_axi_awlen[7]_0 ;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  input wrap_need_to_split_q;
  input [2:0]\m_axi_awlen[2] ;
  input incr_need_to_split_q;
  input \m_axi_awlen[7]_INST_0_i_5 ;
  input access_is_incr_q;
  input \m_axi_awlen[7]_INST_0_i_5_0 ;
  input \gpr1.dout_i_reg[29] ;
  input si_full_size_q;
  input [0:0]\gpr1.dout_i_reg[15] ;
  input [4:0]\gpr1.dout_i_reg[15]_0 ;
  input \gpr1.dout_i_reg[15]_1 ;
  input \gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input \gpr1.dout_i_reg[15]_4 ;
  input [2:0]\m_axi_awlen[2]_INST_0_i_3 ;
  input legal_wrap_len_q;
  input s_axi_wvalid;
  input m_axi_wready;
  input s_axi_wready_0;
  input \current_word_1_reg[4] ;
  input \current_word_1_reg[4]_0 ;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1[4]_i_2 ;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire [0:0]S_AXI_AREADY_I_reg;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire [10:0]\S_AXI_ASIZE_Q_reg[2] ;
  wire \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire \areset_d_reg[0] ;
  wire cmd_b_empty;
  wire cmd_b_push_block;
  wire cmd_b_push_block_reg;
  wire [0:0]cmd_b_push_block_reg_0;
  wire cmd_b_push_block_reg_1;
  wire cmd_push_block;
  wire cmd_push_block_reg;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire command_ongoing_reg_0;
  wire \current_word_1[4]_i_2 ;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire [1:0]\current_word_1_reg[3] ;
  wire \current_word_1_reg[4] ;
  wire \current_word_1_reg[4]_0 ;
  wire [9:0]din;
  wire [18:0]dout;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire full;
  wire [4:0]\goreg_dm.dout_i_reg[18] ;
  wire [0:0]\gpr1.dout_i_reg[15] ;
  wire [4:0]\gpr1.dout_i_reg[15]_0 ;
  wire \gpr1.dout_i_reg[15]_1 ;
  wire \gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire \gpr1.dout_i_reg[15]_4 ;
  wire \gpr1.dout_i_reg[29] ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire [2:0]\m_axi_awlen[2] ;
  wire [2:0]\m_axi_awlen[2]_INST_0_i_3 ;
  wire [7:0]\m_axi_awlen[7] ;
  wire [7:0]\m_axi_awlen[7]_0 ;
  wire \m_axi_awlen[7]_INST_0_i_5 ;
  wire \m_axi_awlen[7]_INST_0_i_5_0 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  wire m_axi_awready;
  wire [0:0]m_axi_awready_0;
  wire [3:0]m_axi_awvalid_INST_0_i_1;
  wire m_axi_wready;
  wire m_axi_wvalid;
  wire out;
  wire s_axi_awvalid;
  wire s_axi_awvalid_0;
  wire [3:0]s_axi_bid;
  wire s_axi_wready;
  wire s_axi_wready_0;
  wire s_axi_wvalid;
  wire [0:0]s_axi_wvalid_0;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wr_en;
  wire wrap_need_to_split_q;

  axi4_dwtrans_axi_data_fifo_v2_1_26_fifo_gen__parameterized0__xdcDup__1 inst
       (.CLK(CLK),
        .D(D),
        .E(E),
        .Q(Q),
        .SR(SR),
        .S_AXI_AREADY_I_reg(S_AXI_AREADY_I_reg),
        .S_AXI_AREADY_I_reg_0(S_AXI_AREADY_I_reg_0),
        .S_AXI_AREADY_I_reg_1(S_AXI_AREADY_I_reg_1),
        .\S_AXI_ASIZE_Q_reg[2] (\S_AXI_ASIZE_Q_reg[2] ),
        .\USE_B_CHANNEL.cmd_b_empty_i_reg (\USE_B_CHANNEL.cmd_b_empty_i_reg ),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(access_is_wrap_q_reg),
        .\areset_d_reg[0] (\areset_d_reg[0] ),
        .cmd_b_empty(cmd_b_empty),
        .cmd_b_push_block(cmd_b_push_block),
        .cmd_b_push_block_reg(cmd_b_push_block_reg),
        .cmd_b_push_block_reg_0(cmd_b_push_block_reg_0),
        .cmd_b_push_block_reg_1(cmd_b_push_block_reg_1),
        .cmd_push_block(cmd_push_block),
        .cmd_push_block_reg(cmd_push_block_reg),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg),
        .command_ongoing_reg_0(command_ongoing_reg_0),
        .\current_word_1[4]_i_2_0 (\current_word_1[4]_i_2 ),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[3] (\current_word_1_reg[3] ),
        .\current_word_1_reg[4] (\current_word_1_reg[4] ),
        .\current_word_1_reg[4]_0 (\current_word_1_reg[4]_0 ),
        .din(din),
        .dout(dout),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(full),
        .\goreg_dm.dout_i_reg[18] (\goreg_dm.dout_i_reg[18] ),
        .\gpr1.dout_i_reg[15] (\gpr1.dout_i_reg[15] ),
        .\gpr1.dout_i_reg[15]_0 (\gpr1.dout_i_reg[15]_0 ),
        .\gpr1.dout_i_reg[15]_1 (\gpr1.dout_i_reg[15]_1 ),
        .\gpr1.dout_i_reg[15]_2 (\gpr1.dout_i_reg[15]_2 ),
        .\gpr1.dout_i_reg[15]_3 (\gpr1.dout_i_reg[15]_3 ),
        .\gpr1.dout_i_reg[15]_4 (\gpr1.dout_i_reg[15]_4 ),
        .\gpr1.dout_i_reg[29] (\gpr1.dout_i_reg[29] ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_awlen[2] (\m_axi_awlen[2] ),
        .\m_axi_awlen[2]_INST_0_i_3_0 (\m_axi_awlen[2]_INST_0_i_3 ),
        .\m_axi_awlen[7] (\m_axi_awlen[7] ),
        .\m_axi_awlen[7]_0 (\m_axi_awlen[7]_0 ),
        .\m_axi_awlen[7]_INST_0_i_5_0 (\m_axi_awlen[7]_INST_0_i_5 ),
        .\m_axi_awlen[7]_INST_0_i_5_1 (\m_axi_awlen[7]_INST_0_i_5_0 ),
        .\m_axi_awlen[7]_INST_0_i_6_0 (\m_axi_awlen[7]_INST_0_i_6 ),
        .\m_axi_awlen[7]_INST_0_i_6_1 (\m_axi_awlen[7]_INST_0_i_6_0 ),
        .m_axi_awready(m_axi_awready),
        .m_axi_awready_0(m_axi_awready_0),
        .m_axi_awvalid_INST_0_i_1_0(m_axi_awvalid_INST_0_i_1),
        .m_axi_wready(m_axi_wready),
        .m_axi_wvalid(m_axi_wvalid),
        .out(out),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_awvalid_0(s_axi_awvalid_0),
        .s_axi_bid(s_axi_bid),
        .s_axi_wready(s_axi_wready),
        .s_axi_wready_0(s_axi_wready_0),
        .s_axi_wvalid(s_axi_wvalid),
        .s_axi_wvalid_0(s_axi_wvalid_0),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(split_ongoing_reg),
        .wr_en(wr_en),
        .wrap_need_to_split_q(wrap_need_to_split_q));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_26_fifo_gen" *) 
module axi4_dwtrans_axi_data_fifo_v2_1_26_fifo_gen
   (dout,
    full,
    empty,
    SR,
    din,
    access_is_incr_q_reg,
    access_is_fix_q_reg,
    \pushed_commands_reg[7] ,
    CLK,
    wr_en,
    \USE_WRITE.wr_cmd_b_ready ,
    out,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    fix_need_to_split_q,
    access_is_incr_q,
    access_is_wrap_q,
    split_ongoing,
    Q,
    \gpr1.dout_i_reg[1] ,
    access_is_fix_q,
    \gpr1.dout_i_reg[1]_0 );
  output [4:0]dout;
  output full;
  output empty;
  output [0:0]SR;
  output [0:0]din;
  output access_is_incr_q_reg;
  output access_is_fix_q_reg;
  output \pushed_commands_reg[7] ;
  input CLK;
  input wr_en;
  input \USE_WRITE.wr_cmd_b_ready ;
  input out;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input fix_need_to_split_q;
  input access_is_incr_q;
  input access_is_wrap_q;
  input split_ongoing;
  input [7:0]Q;
  input [2:0]\gpr1.dout_i_reg[1] ;
  input access_is_fix_q;
  input [3:0]\gpr1.dout_i_reg[1]_0 ;

  wire CLK;
  wire [7:0]Q;
  wire [0:0]SR;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire access_is_fix_q;
  wire access_is_fix_q_reg;
  wire access_is_incr_q;
  wire access_is_incr_q_reg;
  wire access_is_wrap_q;
  wire [0:0]din;
  wire [4:0]dout;
  wire empty;
  wire fix_need_to_split_q;
  wire full;
  wire [2:0]\gpr1.dout_i_reg[1] ;
  wire [3:0]\gpr1.dout_i_reg[1]_0 ;
  wire incr_need_to_split_q;
  wire \m_axi_awlen[7]_INST_0_i_15_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_16_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_17_n_0 ;
  wire out;
  wire [3:0]p_1_out;
  wire \pushed_commands_reg[7] ;
  wire split_ongoing;
  wire wr_en;
  wire wrap_need_to_split_q;
  wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_almost_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED;
  wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_valid_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED;
  wire [7:4]NLW_fifo_gen_inst_dout_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    S_AXI_AREADY_I_i_1
       (.I0(out),
        .O(SR));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "4" *) 
  (* C_AXIS_TID_WIDTH = "8" *) 
  (* C_AXIS_TKEEP_WIDTH = "4" *) 
  (* C_AXIS_TSTRB_WIDTH = "4" *) 
  (* C_AXIS_TUSER_WIDTH = "4" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "2" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "0" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "6" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "9" *) 
  (* C_DIN_WIDTH_AXIS = "1" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "9" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_FULL_FLAGS_RST_VAL = "0" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "0" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "0" *) 
  (* C_HAS_AXIS_TLAST = "0" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "0" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "0" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "0" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_MEMORY_TYPE = "2" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "0" *) 
  (* C_PRELOAD_REGS = "1" *) 
  (* C_PRIM_FIFO_TYPE = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "0" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "6" *) 
  (* C_RD_DEPTH = "32" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "5" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "1" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "6" *) 
  (* C_WR_DEPTH = "32" *) 
  (* C_WR_DEPTH_AXIS = "1024" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "5" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "10" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* is_du_within_envelope = "true" *) 
  axi4_dwtrans_fifo_generator_v13_2_7 fifo_gen_inst
       (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]),
        .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]),
        .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(CLK),
        .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]),
        .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED),
        .din({din,1'b0,1'b0,1'b0,1'b0,p_1_out}),
        .dout({dout[4],NLW_fifo_gen_inst_dout_UNCONNECTED[7:4],dout[3:0]}),
        .empty(empty),
        .full(full),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]),
        .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]),
        .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]),
        .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]),
        .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]),
        .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]),
        .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]),
        .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]),
        .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]),
        .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED),
        .m_axis_tready(1'b0),
        .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]),
        .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]),
        .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED),
        .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]),
        .rd_en(\USE_WRITE.wr_cmd_b_ready ),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED),
        .rst(SR),
        .s_aclk(1'b0),
        .s_aclk_en(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock({1'b0,1'b0}),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock({1'b0,1'b0}),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(1'b0),
        .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tvalid(1'b0),
        .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED),
        .valid(NLW_fifo_gen_inst_valid_UNCONNECTED),
        .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]),
        .wr_en(wr_en),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED));
  LUT4 #(
    .INIT(16'hAAA8)) 
    fifo_gen_inst_i_1__0
       (.I0(access_is_incr_q_reg),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(din));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_2__1
       (.I0(fix_need_to_split_q),
        .I1(\gpr1.dout_i_reg[1]_0 [3]),
        .O(p_1_out[3]));
  LUT4 #(
    .INIT(16'hB888)) 
    fifo_gen_inst_i_3__1
       (.I0(\gpr1.dout_i_reg[1]_0 [2]),
        .I1(fix_need_to_split_q),
        .I2(incr_need_to_split_q),
        .I3(\gpr1.dout_i_reg[1] [2]),
        .O(p_1_out[2]));
  LUT4 #(
    .INIT(16'hB888)) 
    fifo_gen_inst_i_4__1
       (.I0(\gpr1.dout_i_reg[1]_0 [1]),
        .I1(fix_need_to_split_q),
        .I2(incr_need_to_split_q),
        .I3(\gpr1.dout_i_reg[1] [1]),
        .O(p_1_out[1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    fifo_gen_inst_i_5__1
       (.I0(\gpr1.dout_i_reg[1]_0 [0]),
        .I1(fix_need_to_split_q),
        .I2(\gpr1.dout_i_reg[1] [0]),
        .I3(incr_need_to_split_q),
        .I4(wrap_need_to_split_q),
        .O(p_1_out[0]));
  LUT6 #(
    .INIT(64'h00A2A2A200A200A2)) 
    fifo_gen_inst_i_8
       (.I0(access_is_fix_q_reg),
        .I1(access_is_incr_q),
        .I2(\pushed_commands_reg[7] ),
        .I3(access_is_wrap_q),
        .I4(split_ongoing),
        .I5(wrap_need_to_split_q),
        .O(access_is_incr_q_reg));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDDD5)) 
    \m_axi_awlen[7]_INST_0_i_12 
       (.I0(access_is_fix_q),
        .I1(fix_need_to_split_q),
        .I2(\m_axi_awlen[7]_INST_0_i_15_n_0 ),
        .I3(\m_axi_awlen[7]_INST_0_i_16_n_0 ),
        .I4(Q[7]),
        .I5(Q[6]),
        .O(access_is_fix_q_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \m_axi_awlen[7]_INST_0_i_13 
       (.I0(Q[7]),
        .I1(Q[6]),
        .I2(\m_axi_awlen[7]_INST_0_i_17_n_0 ),
        .I3(Q[3]),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(\pushed_commands_reg[7] ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    \m_axi_awlen[7]_INST_0_i_15 
       (.I0(\gpr1.dout_i_reg[1]_0 [3]),
        .I1(Q[3]),
        .I2(Q[5]),
        .I3(Q[4]),
        .O(\m_axi_awlen[7]_INST_0_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_awlen[7]_INST_0_i_16 
       (.I0(Q[1]),
        .I1(\gpr1.dout_i_reg[1]_0 [1]),
        .I2(Q[2]),
        .I3(\gpr1.dout_i_reg[1]_0 [2]),
        .I4(\gpr1.dout_i_reg[1]_0 [0]),
        .I5(Q[0]),
        .O(\m_axi_awlen[7]_INST_0_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_awlen[7]_INST_0_i_17 
       (.I0(\gpr1.dout_i_reg[1] [0]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(\gpr1.dout_i_reg[1] [2]),
        .I4(Q[1]),
        .I5(\gpr1.dout_i_reg[1] [1]),
        .O(\m_axi_awlen[7]_INST_0_i_17_n_0 ));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_26_fifo_gen" *) 
module axi4_dwtrans_axi_data_fifo_v2_1_26_fifo_gen__parameterized0
   (dout,
    din,
    wr_en,
    D,
    s_axi_arvalid_0,
    m_axi_arready_0,
    command_ongoing_reg,
    m_axi_arready_1,
    empty_fwft_i_reg,
    empty_fwft_i_reg_0,
    empty_fwft_i_reg_1,
    s_axi_rdata,
    m_axi_arready_2,
    m_axi_rvalid_0,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    s_axi_aresetn,
    \goreg_dm.dout_i_reg[18] ,
    \goreg_dm.dout_i_reg[2] ,
    s_axi_rvalid,
    m_axi_rready,
    p_0_in,
    s_axi_rlast,
    cmd_empty_reg,
    CLK,
    SR,
    \m_axi_arsize[0] ,
    Q,
    fix_need_to_split_q,
    \m_axi_arlen[7]_INST_0_i_1_0 ,
    access_is_wrap_q,
    split_ongoing,
    s_axi_arvalid,
    E,
    areset_d,
    command_ongoing,
    m_axi_arready,
    out,
    cmd_push_block,
    s_axi_rready,
    m_axi_rvalid,
    p_1_in,
    m_axi_rdata,
    \cmd_depth_reg[5] ,
    cmd_empty,
    s_axi_rid,
    m_axi_arvalid,
    access_is_fix_q,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    \m_axi_arlen[7] ,
    \m_axi_arlen[7]_0 ,
    \m_axi_arlen[7]_INST_0_i_1_1 ,
    \m_axi_arlen[2] ,
    access_is_incr_q,
    \m_axi_arlen[7]_INST_0_i_8_0 ,
    \m_axi_arlen[7]_INST_0_i_13_0 ,
    \gpr1.dout_i_reg[29] ,
    si_full_size_q,
    \gpr1.dout_i_reg[15] ,
    \gpr1.dout_i_reg[15]_0 ,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \gpr1.dout_i_reg[15]_4 ,
    \m_axi_arlen[2]_INST_0_i_3_0 ,
    legal_wrap_len_q,
    first_mi_word,
    s_axi_rvalid_0,
    s_axi_rvalid_1,
    \current_word_1_reg[3] ,
    s_axi_rdata_0_sp_1,
    \current_word_1_reg[4] ,
    \current_word_1_reg[3]_0 ,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[2] ,
    m_axi_rlast,
    cmd_empty_reg_0);
  output [20:0]dout;
  output [11:0]din;
  output wr_en;
  output [4:0]D;
  output s_axi_arvalid_0;
  output m_axi_arready_0;
  output command_ongoing_reg;
  output m_axi_arready_1;
  output [0:0]empty_fwft_i_reg;
  output [0:0]empty_fwft_i_reg_0;
  output [0:0]empty_fwft_i_reg_1;
  output [255:0]s_axi_rdata;
  output [0:0]m_axi_arready_2;
  output [0:0]m_axi_rvalid_0;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output [0:0]s_axi_aresetn;
  output \goreg_dm.dout_i_reg[18] ;
  output \goreg_dm.dout_i_reg[2] ;
  output s_axi_rvalid;
  output m_axi_rready;
  output [3:0]p_0_in;
  output s_axi_rlast;
  output cmd_empty_reg;
  input CLK;
  input [0:0]SR;
  input [8:0]\m_axi_arsize[0] ;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  input access_is_wrap_q;
  input split_ongoing;
  input s_axi_arvalid;
  input [0:0]E;
  input [1:0]areset_d;
  input command_ongoing;
  input m_axi_arready;
  input out;
  input cmd_push_block;
  input s_axi_rready;
  input m_axi_rvalid;
  input [255:0]p_1_in;
  input [127:0]m_axi_rdata;
  input \cmd_depth_reg[5] ;
  input cmd_empty;
  input [3:0]s_axi_rid;
  input [3:0]m_axi_arvalid;
  input access_is_fix_q;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input [7:0]\m_axi_arlen[7] ;
  input [7:0]\m_axi_arlen[7]_0 ;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1_1 ;
  input [2:0]\m_axi_arlen[2] ;
  input access_is_incr_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_8_0 ;
  input [2:0]\m_axi_arlen[7]_INST_0_i_13_0 ;
  input \gpr1.dout_i_reg[29] ;
  input si_full_size_q;
  input [0:0]\gpr1.dout_i_reg[15] ;
  input [4:0]\gpr1.dout_i_reg[15]_0 ;
  input \gpr1.dout_i_reg[15]_1 ;
  input \gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input \gpr1.dout_i_reg[15]_4 ;
  input [2:0]\m_axi_arlen[2]_INST_0_i_3_0 ;
  input legal_wrap_len_q;
  input first_mi_word;
  input [0:0]s_axi_rvalid_0;
  input s_axi_rvalid_1;
  input \current_word_1_reg[3] ;
  input s_axi_rdata_0_sp_1;
  input \current_word_1_reg[4] ;
  input \current_word_1_reg[3]_0 ;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1_reg[2] ;
  input m_axi_rlast;
  input cmd_empty_reg_0;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire [4:0]\USE_READ.rd_cmd_mask ;
  wire [4:0]\USE_READ.rd_cmd_offset ;
  wire \USE_READ.rd_cmd_ready ;
  wire \USE_READ.rd_cmd_split ;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire [1:0]areset_d;
  wire \cmd_depth[5]_i_3_n_0 ;
  wire \cmd_depth[5]_i_4_n_0 ;
  wire \cmd_depth[5]_i_5_n_0 ;
  wire \cmd_depth_reg[5] ;
  wire cmd_empty;
  wire cmd_empty0;
  wire cmd_empty_reg;
  wire cmd_empty_reg_0;
  wire cmd_push_block;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire \current_word_1[2]_i_3_n_0 ;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire \current_word_1_reg[3] ;
  wire \current_word_1_reg[3]_0 ;
  wire \current_word_1_reg[4] ;
  wire [11:0]din;
  wire [20:0]dout;
  wire empty;
  wire [0:0]empty_fwft_i_reg;
  wire [0:0]empty_fwft_i_reg_0;
  wire [0:0]empty_fwft_i_reg_1;
  wire fifo_gen_inst_i_14__0_n_0;
  wire fifo_gen_inst_i_15__0_n_0;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire full;
  wire \goreg_dm.dout_i_reg[18] ;
  wire \goreg_dm.dout_i_reg[2] ;
  wire [0:0]\gpr1.dout_i_reg[15] ;
  wire [4:0]\gpr1.dout_i_reg[15]_0 ;
  wire \gpr1.dout_i_reg[15]_1 ;
  wire \gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire \gpr1.dout_i_reg[15]_4 ;
  wire \gpr1.dout_i_reg[29] ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire \m_axi_arlen[0]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_5_n_0 ;
  wire [2:0]\m_axi_arlen[2] ;
  wire \m_axi_arlen[2]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[2]_INST_0_i_2_n_0 ;
  wire [2:0]\m_axi_arlen[2]_INST_0_i_3_0 ;
  wire \m_axi_arlen[2]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[2]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_5_n_0 ;
  wire \m_axi_arlen[4]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[4]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[4]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[6]_INST_0_i_1_n_0 ;
  wire [7:0]\m_axi_arlen[7] ;
  wire [7:0]\m_axi_arlen[7]_0 ;
  wire \m_axi_arlen[7]_INST_0_i_10_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_11_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_12_n_0 ;
  wire [2:0]\m_axi_arlen[7]_INST_0_i_13_0 ;
  wire \m_axi_arlen[7]_INST_0_i_13_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_14_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_15_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_16_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_17_n_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1_1 ;
  wire \m_axi_arlen[7]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_5_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_6_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_7_n_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_8_0 ;
  wire \m_axi_arlen[7]_INST_0_i_8_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_9_n_0 ;
  wire m_axi_arready;
  wire m_axi_arready_0;
  wire m_axi_arready_1;
  wire [0:0]m_axi_arready_2;
  wire [8:0]\m_axi_arsize[0] ;
  wire [3:0]m_axi_arvalid;
  wire m_axi_arvalid_INST_0_i_1_n_0;
  wire m_axi_arvalid_INST_0_i_2_n_0;
  wire [127:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire m_axi_rready_INST_0_i_1_n_0;
  wire m_axi_rvalid;
  wire [0:0]m_axi_rvalid_0;
  wire out;
  wire [3:0]p_0_in;
  wire [31:19]p_0_out;
  wire [255:0]p_1_in;
  wire [0:0]s_axi_aresetn;
  wire s_axi_arvalid;
  wire s_axi_arvalid_0;
  wire [255:0]s_axi_rdata;
  wire \s_axi_rdata[127]_INST_0_i_1_n_0 ;
  wire \s_axi_rdata[255]_INST_0_i_1_n_0 ;
  wire \s_axi_rdata[255]_INST_0_i_3_n_0 ;
  wire s_axi_rdata_0_sn_1;
  wire [3:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire s_axi_rvalid;
  wire [0:0]s_axi_rvalid_0;
  wire s_axi_rvalid_1;
  wire s_axi_rvalid_INST_0_i_1_n_0;
  wire s_axi_rvalid_INST_0_i_4_n_0;
  wire s_axi_rvalid_INST_0_i_7_n_0;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wr_en;
  wire wrap_need_to_split_q;
  wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_almost_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED;
  wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_valid_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED;

  assign s_axi_rdata_0_sn_1 = s_axi_rdata_0_sp_1;
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h08)) 
    S_AXI_AREADY_I_i_2__0
       (.I0(m_axi_arready),
        .I1(command_ongoing_reg),
        .I2(fifo_gen_inst_i_14__0_n_0),
        .O(m_axi_arready_0));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT5 #(
    .INIT(32'h55755555)) 
    \WORD_LANE[0].S_AXI_RDATA_II[127]_i_1 
       (.I0(out),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(m_axi_rvalid),
        .I3(empty),
        .I4(s_axi_rready),
        .O(s_axi_aresetn));
  LUT5 #(
    .INIT(32'h00005400)) 
    \WORD_LANE[0].S_AXI_RDATA_II[127]_i_2 
       (.I0(empty),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(s_axi_rready),
        .I3(m_axi_rvalid),
        .I4(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .O(empty_fwft_i_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT5 #(
    .INIT(32'h54000000)) 
    \WORD_LANE[1].S_AXI_RDATA_II[255]_i_1 
       (.I0(empty),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(s_axi_rready),
        .I3(m_axi_rvalid),
        .I4(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .O(empty_fwft_i_reg_0));
  LUT3 #(
    .INIT(8'h69)) 
    \cmd_depth[1]_i_1 
       (.I0(Q[0]),
        .I1(cmd_empty0),
        .I2(Q[1]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT4 #(
    .INIT(16'h78E1)) 
    \cmd_depth[2]_i_1 
       (.I0(cmd_empty0),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT5 #(
    .INIT(32'h7FFE8001)) 
    \cmd_depth[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(cmd_empty0),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \cmd_depth[4]_i_1 
       (.I0(Q[4]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(cmd_empty0),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hAAAAA2AAAAAAAAAA)) 
    \cmd_depth[4]_i_2 
       (.I0(wr_en),
        .I1(s_axi_rready),
        .I2(empty),
        .I3(m_axi_rvalid),
        .I4(m_axi_rready_INST_0_i_1_n_0),
        .I5(\cmd_depth_reg[5] ),
        .O(cmd_empty0));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cmd_depth[5]_i_1 
       (.I0(\USE_READ.rd_cmd_ready ),
        .I1(wr_en),
        .O(m_axi_rvalid_0));
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \cmd_depth[5]_i_2 
       (.I0(Q[5]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\cmd_depth[5]_i_3_n_0 ),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hD0000000FFFFFFD0)) 
    \cmd_depth[5]_i_3 
       (.I0(\cmd_depth_reg[5] ),
        .I1(\cmd_depth[5]_i_4_n_0 ),
        .I2(wr_en),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cmd_depth[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDFDFDFFFD)) 
    \cmd_depth[5]_i_4 
       (.I0(s_axi_rready),
        .I1(\cmd_depth[5]_i_5_n_0 ),
        .I2(s_axi_rvalid_INST_0_i_4_n_0),
        .I3(\goreg_dm.dout_i_reg[18] ),
        .I4(\goreg_dm.dout_i_reg[2] ),
        .I5(s_axi_rvalid_INST_0_i_1_n_0),
        .O(\cmd_depth[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cmd_depth[5]_i_5 
       (.I0(empty),
        .I1(m_axi_rvalid),
        .O(\cmd_depth[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'hCB08)) 
    cmd_empty_i_1
       (.I0(cmd_empty_reg_0),
        .I1(\USE_READ.rd_cmd_ready ),
        .I2(wr_en),
        .I3(cmd_empty),
        .O(cmd_empty_reg));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'h70705000)) 
    cmd_push_block_i_1__0
       (.I0(m_axi_arready),
        .I1(command_ongoing_reg),
        .I2(out),
        .I3(wr_en),
        .I4(cmd_push_block),
        .O(m_axi_arready_1));
  LUT6 #(
    .INIT(64'h8FFF8F8F88008888)) 
    command_ongoing_i_1__0
       (.I0(s_axi_arvalid),
        .I1(E),
        .I2(m_axi_arready_0),
        .I3(areset_d[0]),
        .I4(areset_d[1]),
        .I5(command_ongoing),
        .O(s_axi_arvalid_0));
  LUT5 #(
    .INIT(32'h88888882)) 
    \current_word_1[0]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [0]),
        .I1(\current_word_1_reg[1] ),
        .I2(dout[13]),
        .I3(dout[12]),
        .I4(dout[11]),
        .O(p_0_in[0]));
  LUT6 #(
    .INIT(64'h8888828288888288)) 
    \current_word_1[1]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [1]),
        .I1(\current_word_1_reg[1]_0 ),
        .I2(dout[13]),
        .I3(dout[11]),
        .I4(dout[12]),
        .I5(\current_word_1_reg[1] ),
        .O(p_0_in[1]));
  LUT6 #(
    .INIT(64'hAA8A00200020AA8A)) 
    \current_word_1[2]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [2]),
        .I1(dout[13]),
        .I2(dout[12]),
        .I3(dout[11]),
        .I4(\current_word_1_reg[2] ),
        .I5(\current_word_1[2]_i_3_n_0 ),
        .O(p_0_in[2]));
  LUT5 #(
    .INIT(32'hFFDDFFDF)) 
    \current_word_1[2]_i_3 
       (.I0(\current_word_1_reg[1]_0 ),
        .I1(dout[12]),
        .I2(dout[11]),
        .I3(dout[13]),
        .I4(\current_word_1_reg[1] ),
        .O(\current_word_1[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h2282222288288888)) 
    \current_word_1[3]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [3]),
        .I1(\current_word_1_reg[3] ),
        .I2(dout[11]),
        .I3(dout[13]),
        .I4(dout[12]),
        .I5(\current_word_1_reg[3]_0 ),
        .O(p_0_in[3]));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "4" *) 
  (* C_AXIS_TID_WIDTH = "8" *) 
  (* C_AXIS_TKEEP_WIDTH = "4" *) 
  (* C_AXIS_TSTRB_WIDTH = "4" *) 
  (* C_AXIS_TUSER_WIDTH = "4" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "2" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "0" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "6" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "32" *) 
  (* C_DIN_WIDTH_AXIS = "1" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "32" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_FULL_FLAGS_RST_VAL = "0" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "0" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "0" *) 
  (* C_HAS_AXIS_TLAST = "0" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "0" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "0" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "0" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_MEMORY_TYPE = "2" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "0" *) 
  (* C_PRELOAD_REGS = "1" *) 
  (* C_PRIM_FIFO_TYPE = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "0" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "6" *) 
  (* C_RD_DEPTH = "32" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "5" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "1" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "6" *) 
  (* C_WR_DEPTH = "32" *) 
  (* C_WR_DEPTH_AXIS = "1024" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "5" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "10" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* is_du_within_envelope = "true" *) 
  axi4_dwtrans_fifo_generator_v13_2_7__parameterized0 fifo_gen_inst
       (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]),
        .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]),
        .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(CLK),
        .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]),
        .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED),
        .din({p_0_out[31],din[11],\m_axi_arsize[0] [8],p_0_out[28:19],\m_axi_arsize[0] [7:3],din[10:0],\m_axi_arsize[0] [2:0]}),
        .dout({dout[20],\USE_READ.rd_cmd_split ,dout[19:14],\USE_READ.rd_cmd_offset ,\USE_READ.rd_cmd_mask ,dout[13:0]}),
        .empty(empty),
        .full(full),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]),
        .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]),
        .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]),
        .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]),
        .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]),
        .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]),
        .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]),
        .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]),
        .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]),
        .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED),
        .m_axis_tready(1'b0),
        .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]),
        .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]),
        .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED),
        .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]),
        .rd_en(\USE_READ.rd_cmd_ready ),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED),
        .rst(SR),
        .s_aclk(1'b0),
        .s_aclk_en(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock({1'b0,1'b0}),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock({1'b0,1'b0}),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(1'b0),
        .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tvalid(1'b0),
        .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED),
        .valid(NLW_fifo_gen_inst_valid_UNCONNECTED),
        .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]),
        .wr_en(wr_en),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_10__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_3 ),
        .I3(\gpr1.dout_i_reg[15]_0 [2]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [5]),
        .O(p_0_out[21]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_11__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_2 ),
        .I3(\gpr1.dout_i_reg[15]_0 [1]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [4]),
        .O(p_0_out[20]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_12__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_1 ),
        .I3(\gpr1.dout_i_reg[15]_0 [0]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [3]),
        .O(p_0_out[19]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    fifo_gen_inst_i_13__0
       (.I0(\cmd_depth_reg[5] ),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(m_axi_rvalid),
        .I3(empty),
        .I4(s_axi_rready),
        .O(\USE_READ.rd_cmd_ready ));
  LUT6 #(
    .INIT(64'h00A2A2A200A200A2)) 
    fifo_gen_inst_i_14__0
       (.I0(\m_axi_arlen[7]_INST_0_i_12_n_0 ),
        .I1(access_is_incr_q),
        .I2(\m_axi_arlen[7]_INST_0_i_13_n_0 ),
        .I3(access_is_wrap_q),
        .I4(split_ongoing),
        .I5(wrap_need_to_split_q),
        .O(fifo_gen_inst_i_14__0_n_0));
  LUT6 #(
    .INIT(64'h0040CCCC4444CCCC)) 
    fifo_gen_inst_i_15__0
       (.I0(access_is_wrap_q),
        .I1(\gpr1.dout_i_reg[15]_0 [4]),
        .I2(\gpr1.dout_i_reg[15] ),
        .I3(si_full_size_q),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(fifo_gen_inst_i_15__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_16
       (.I0(split_ongoing),
        .I1(access_is_incr_q),
        .O(split_ongoing_reg));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_17
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .O(access_is_wrap_q_reg));
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_1__1
       (.I0(access_is_fix_q),
        .I1(\m_axi_arsize[0] [8]),
        .O(p_0_out[31]));
  LUT4 #(
    .INIT(16'hAAA8)) 
    fifo_gen_inst_i_2__0
       (.I0(fifo_gen_inst_i_14__0_n_0),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(din[11]));
  LUT3 #(
    .INIT(8'h80)) 
    fifo_gen_inst_i_3__0
       (.I0(fifo_gen_inst_i_15__0_n_0),
        .I1(\m_axi_arsize[0] [7]),
        .I2(\gpr1.dout_i_reg[29] ),
        .O(p_0_out[28]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_4__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [3]),
        .I3(access_is_wrap_q_reg),
        .I4(\m_axi_arsize[0] [6]),
        .I5(\gpr1.dout_i_reg[15]_4 ),
        .O(p_0_out[27]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_5__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [2]),
        .I3(access_is_wrap_q_reg),
        .I4(\m_axi_arsize[0] [5]),
        .I5(\gpr1.dout_i_reg[15]_3 ),
        .O(p_0_out[26]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_6__1
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [1]),
        .I3(access_is_wrap_q_reg),
        .I4(\m_axi_arsize[0] [4]),
        .I5(\gpr1.dout_i_reg[15]_2 ),
        .O(p_0_out[25]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_7__1
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [0]),
        .I3(access_is_wrap_q_reg),
        .I4(\m_axi_arsize[0] [3]),
        .I5(\gpr1.dout_i_reg[15]_1 ),
        .O(p_0_out[24]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_8__1
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15] ),
        .I3(\gpr1.dout_i_reg[15]_0 [4]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [7]),
        .O(p_0_out[23]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_9__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_4 ),
        .I3(\gpr1.dout_i_reg[15]_0 [3]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [6]),
        .O(p_0_out[22]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h5400)) 
    first_word_i_1__0
       (.I0(empty),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(s_axi_rready),
        .I3(m_axi_rvalid),
        .O(empty_fwft_i_reg));
  LUT6 #(
    .INIT(64'hF704F7F708FB0808)) 
    \m_axi_arlen[0]_INST_0 
       (.I0(\m_axi_arlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[2] [0]),
        .I5(\m_axi_arlen[0]_INST_0_i_1_n_0 ),
        .O(din[0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[0]_INST_0_i_1 
       (.I0(\m_axi_arlen[7]_0 [0]),
        .I1(\m_axi_arsize[0] [8]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [0]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I4(\m_axi_arlen[1]_INST_0_i_3_n_0 ),
        .O(\m_axi_arlen[0]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0BFBF404F4040BFB)) 
    \m_axi_arlen[1]_INST_0 
       (.I0(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .I1(\m_axi_arlen[2] [1]),
        .I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[7] [1]),
        .I4(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
        .O(din[1]));
  LUT6 #(
    .INIT(64'h00000000001DFF1D)) 
    \m_axi_arlen[1]_INST_0_i_1 
       (.I0(\m_axi_arlen[1]_INST_0_i_3_n_0 ),
        .I1(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [0]),
        .I3(\m_axi_arsize[0] [8]),
        .I4(\m_axi_arlen[7]_0 [0]),
        .I5(\m_axi_arlen[1]_INST_0_i_4_n_0 ),
        .O(\m_axi_arlen[1]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h47444777)) 
    \m_axi_arlen[1]_INST_0_i_2 
       (.I0(\m_axi_arlen[7]_0 [1]),
        .I1(\m_axi_arsize[0] [8]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [1]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I4(\m_axi_arlen[1]_INST_0_i_5_n_0 ),
        .O(\m_axi_arlen[1]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[1]_INST_0_i_3 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [0]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[2]_INST_0_i_3_0 [0]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[1]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hF704F7F7)) 
    \m_axi_arlen[1]_INST_0_i_4 
       (.I0(\m_axi_arlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[2] [0]),
        .O(\m_axi_arlen[1]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[1]_INST_0_i_5 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [1]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[2]_INST_0_i_3_0 [1]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[1]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_arlen[2]_INST_0 
       (.I0(\m_axi_arlen[2]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7] [2]),
        .I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[2] [2]),
        .I4(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .I5(\m_axi_arlen[2]_INST_0_i_3_n_0 ),
        .O(din[2]));
  LUT6 #(
    .INIT(64'hFFFF88B888B80000)) 
    \m_axi_arlen[2]_INST_0_i_1 
       (.I0(\m_axi_arlen[7] [1]),
        .I1(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I2(\m_axi_arlen[2] [1]),
        .I3(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[2]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'h0000FD0D)) 
    \m_axi_arlen[2]_INST_0_i_2 
       (.I0(access_is_incr_q),
        .I1(\m_axi_arsize[0] [8]),
        .I2(incr_need_to_split_q),
        .I3(split_ongoing),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[2]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_arlen[2]_INST_0_i_3 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_1 [2]),
        .I1(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I2(\m_axi_arlen[2]_INST_0_i_4_n_0 ),
        .I3(\m_axi_arlen[7]_0 [2]),
        .I4(\m_axi_arsize[0] [8]),
        .O(\m_axi_arlen[2]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[2]_INST_0_i_4 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [2]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[2]_INST_0_i_3_0 [2]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[2]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_arlen[3]_INST_0 
       (.I0(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7] [3]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
        .O(din[3]));
  LUT5 #(
    .INIT(32'hBBB2B222)) 
    \m_axi_arlen[3]_INST_0_i_1 
       (.I0(\m_axi_arlen[3]_INST_0_i_3_n_0 ),
        .I1(\m_axi_arlen[2]_INST_0_i_3_n_0 ),
        .I2(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
        .I3(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
        .I4(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
        .O(\m_axi_arlen[3]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[3]_INST_0_i_2 
       (.I0(\m_axi_arlen[7]_0 [3]),
        .I1(\m_axi_arsize[0] [8]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [3]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I4(\m_axi_arlen[3]_INST_0_i_5_n_0 ),
        .O(\m_axi_arlen[3]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_arlen[3]_INST_0_i_3 
       (.I0(\m_axi_arlen[7] [2]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[2] [2]),
        .I4(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[3]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_arlen[3]_INST_0_i_4 
       (.I0(\m_axi_arlen[7] [1]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[2] [1]),
        .I4(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[3]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_arlen[3]_INST_0_i_5 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_arlen[7]_INST_0_i_1_0 [3]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_arlen[3]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_arlen[4]_INST_0 
       (.I0(\m_axi_arlen[4]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7] [4]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .O(din[4]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT5 #(
    .INIT(32'h2000FF20)) 
    \m_axi_arlen[4]_INST_0_i_1 
       (.I0(\m_axi_arlen[7] [3]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .I3(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
        .I4(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[4]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[4]_INST_0_i_2 
       (.I0(\m_axi_arlen[7]_0 [4]),
        .I1(\m_axi_arsize[0] [8]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [4]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I4(\m_axi_arlen[4]_INST_0_i_3_n_0 ),
        .O(\m_axi_arlen[4]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_arlen[4]_INST_0_i_3 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_arlen[7]_INST_0_i_1_0 [4]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_arlen[4]_INST_0_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_arlen[5]_INST_0 
       (.I0(\m_axi_arlen[7]_INST_0_i_4_n_0 ),
        .I1(\m_axi_arlen[7] [5]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_arlen[7]_INST_0_i_5_n_0 ),
        .O(din[5]));
  LUT6 #(
    .INIT(64'hD42BBBBB2BD44444)) 
    \m_axi_arlen[6]_INST_0 
       (.I0(\m_axi_arlen[7]_INST_0_i_5_n_0 ),
        .I1(\m_axi_arlen[7]_INST_0_i_4_n_0 ),
        .I2(\m_axi_arlen[7] [5]),
        .I3(\m_axi_arlen[7] [6]),
        .I4(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I5(\m_axi_arlen[7]_INST_0_i_6_n_0 ),
        .O(din[6]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \m_axi_arlen[6]_INST_0_i_1 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .O(\m_axi_arlen[6]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h95559995A999AAA9)) 
    \m_axi_arlen[7]_INST_0 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
        .I2(\m_axi_arlen[7]_INST_0_i_3_n_0 ),
        .I3(\m_axi_arlen[7]_INST_0_i_4_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_5_n_0 ),
        .I5(\m_axi_arlen[7]_INST_0_i_6_n_0 ),
        .O(din[7]));
  LUT6 #(
    .INIT(64'h202020DFDFDF20DF)) 
    \m_axi_arlen[7]_INST_0_i_1 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .I2(\m_axi_arlen[7] [7]),
        .I3(\m_axi_arlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_arsize[0] [8]),
        .I5(\m_axi_arlen[7]_0 [7]),
        .O(\m_axi_arlen[7]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_arlen[7]_INST_0_i_10 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_arlen[7]_INST_0_i_1_0 [6]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_arlen[7]_INST_0_i_11 
       (.I0(access_is_wrap_q),
        .I1(legal_wrap_len_q),
        .I2(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDDD5)) 
    \m_axi_arlen[7]_INST_0_i_12 
       (.I0(access_is_fix_q),
        .I1(fix_need_to_split_q),
        .I2(\m_axi_arlen[7]_INST_0_i_8_0 [7]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_0 [6]),
        .I4(\m_axi_arlen[7]_INST_0_i_15_n_0 ),
        .I5(\m_axi_arlen[7]_INST_0_i_16_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \m_axi_arlen[7]_INST_0_i_13 
       (.I0(\m_axi_arlen[7]_INST_0_i_8_0 [7]),
        .I1(\m_axi_arlen[7]_INST_0_i_8_0 [6]),
        .I2(\m_axi_arlen[7]_INST_0_i_17_n_0 ),
        .I3(\m_axi_arlen[7]_INST_0_i_8_0 [3]),
        .I4(\m_axi_arlen[7]_INST_0_i_8_0 [5]),
        .I5(\m_axi_arlen[7]_INST_0_i_8_0 [4]),
        .O(\m_axi_arlen[7]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_arlen[7]_INST_0_i_14 
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_arlen[7]_INST_0_i_14_n_0 ));
  LUT4 #(
    .INIT(16'hFFF6)) 
    \m_axi_arlen[7]_INST_0_i_15 
       (.I0(\m_axi_arlen[7]_0 [3]),
        .I1(\m_axi_arlen[7]_INST_0_i_8_0 [3]),
        .I2(\m_axi_arlen[7]_INST_0_i_8_0 [5]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_0 [4]),
        .O(\m_axi_arlen[7]_INST_0_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_arlen[7]_INST_0_i_16 
       (.I0(\m_axi_arlen[7]_INST_0_i_8_0 [1]),
        .I1(\m_axi_arlen[7]_0 [1]),
        .I2(\m_axi_arlen[7]_INST_0_i_8_0 [2]),
        .I3(\m_axi_arlen[7]_0 [2]),
        .I4(\m_axi_arlen[7]_0 [0]),
        .I5(\m_axi_arlen[7]_INST_0_i_8_0 [0]),
        .O(\m_axi_arlen[7]_INST_0_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_arlen[7]_INST_0_i_17 
       (.I0(\m_axi_arlen[7]_INST_0_i_13_0 [0]),
        .I1(\m_axi_arlen[7]_INST_0_i_8_0 [0]),
        .I2(\m_axi_arlen[7]_INST_0_i_8_0 [1]),
        .I3(\m_axi_arlen[7]_INST_0_i_13_0 [1]),
        .I4(\m_axi_arlen[7]_INST_0_i_8_0 [2]),
        .I5(\m_axi_arlen[7]_INST_0_i_13_0 [2]),
        .O(\m_axi_arlen[7]_INST_0_i_17_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_arlen[7]_INST_0_i_2 
       (.I0(\m_axi_arlen[7] [6]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_arlen[7]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_arlen[7]_INST_0_i_3 
       (.I0(\m_axi_arlen[7] [5]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_arlen[7]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8000A080E0A0FFE0)) 
    \m_axi_arlen[7]_INST_0_i_4 
       (.I0(\m_axi_arlen[7] [4]),
        .I1(\m_axi_arlen[7] [3]),
        .I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
        .I4(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
        .I5(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[7]_INST_0_i_5 
       (.I0(\m_axi_arlen[7]_0 [5]),
        .I1(\m_axi_arsize[0] [8]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [5]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_9_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[7]_INST_0_i_6 
       (.I0(\m_axi_arlen[7]_0 [6]),
        .I1(\m_axi_arsize[0] [8]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [6]),
        .I3(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h8B888B8B8B8B8B8B)) 
    \m_axi_arlen[7]_INST_0_i_7 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_1 [7]),
        .I1(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I2(fix_need_to_split_q),
        .I3(\m_axi_arlen[7]_INST_0_i_1_0 [7]),
        .I4(access_is_wrap_q),
        .I5(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAFFAABFAAFFAA)) 
    \m_axi_arlen[7]_INST_0_i_8 
       (.I0(\m_axi_arlen[7]_INST_0_i_11_n_0 ),
        .I1(incr_need_to_split_q),
        .I2(\m_axi_arlen[7]_INST_0_i_12_n_0 ),
        .I3(access_is_incr_q),
        .I4(\m_axi_arlen[7]_INST_0_i_13_n_0 ),
        .I5(\m_axi_arlen[7]_INST_0_i_14_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_arlen[7]_INST_0_i_9 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_arlen[7]_INST_0_i_1_0 [5]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_arsize[0]_INST_0 
       (.I0(\m_axi_arsize[0] [8]),
        .I1(\m_axi_arsize[0] [0]),
        .O(din[8]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_arsize[1]_INST_0 
       (.I0(\m_axi_arsize[0] [8]),
        .I1(\m_axi_arsize[0] [1]),
        .O(din[9]));
  LUT2 #(
    .INIT(4'hB)) 
    \m_axi_arsize[2]_INST_0 
       (.I0(\m_axi_arsize[0] [2]),
        .I1(\m_axi_arsize[0] [8]),
        .O(din[10]));
  LUT6 #(
    .INIT(64'h8A8A8A8A88888A88)) 
    m_axi_arvalid_INST_0
       (.I0(command_ongoing),
        .I1(cmd_push_block),
        .I2(full),
        .I3(m_axi_arvalid_INST_0_i_1_n_0),
        .I4(m_axi_arvalid_INST_0_i_2_n_0),
        .I5(cmd_empty),
        .O(command_ongoing_reg));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    m_axi_arvalid_INST_0_i_1
       (.I0(m_axi_arvalid[0]),
        .I1(s_axi_rid[0]),
        .I2(s_axi_rid[1]),
        .I3(m_axi_arvalid[1]),
        .I4(s_axi_rid[2]),
        .I5(m_axi_arvalid[2]),
        .O(m_axi_arvalid_INST_0_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_arvalid_INST_0_i_2
       (.I0(s_axi_rid[3]),
        .I1(m_axi_arvalid[3]),
        .O(m_axi_arvalid_INST_0_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'h54)) 
    m_axi_rready_INST_0
       (.I0(empty),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(s_axi_rready),
        .O(m_axi_rready));
  LUT6 #(
    .INIT(64'h00000000000000AE)) 
    m_axi_rready_INST_0_i_1
       (.I0(s_axi_rvalid_INST_0_i_4_n_0),
        .I1(\goreg_dm.dout_i_reg[18] ),
        .I2(\goreg_dm.dout_i_reg[2] ),
        .I3(dout[20]),
        .I4(dout[19]),
        .I5(\cmd_depth_reg[5] ),
        .O(m_axi_rready_INST_0_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \queue_id[3]_i_1__0 
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .O(wr_en));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[0]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[0]),
        .I3(m_axi_rdata[0]),
        .O(s_axi_rdata[0]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[100]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[100]),
        .I3(m_axi_rdata[100]),
        .O(s_axi_rdata[100]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[101]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[101]),
        .I3(m_axi_rdata[101]),
        .O(s_axi_rdata[101]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[102]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[102]),
        .I3(m_axi_rdata[102]),
        .O(s_axi_rdata[102]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[103]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[103]),
        .I3(m_axi_rdata[103]),
        .O(s_axi_rdata[103]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[104]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[104]),
        .I3(m_axi_rdata[104]),
        .O(s_axi_rdata[104]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[105]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[105]),
        .I3(m_axi_rdata[105]),
        .O(s_axi_rdata[105]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[106]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[106]),
        .I3(m_axi_rdata[106]),
        .O(s_axi_rdata[106]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[107]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[107]),
        .I3(m_axi_rdata[107]),
        .O(s_axi_rdata[107]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[108]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[108]),
        .I3(m_axi_rdata[108]),
        .O(s_axi_rdata[108]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[109]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[109]),
        .I3(m_axi_rdata[109]),
        .O(s_axi_rdata[109]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[10]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[10]),
        .I3(m_axi_rdata[10]),
        .O(s_axi_rdata[10]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[110]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[110]),
        .I3(m_axi_rdata[110]),
        .O(s_axi_rdata[110]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[111]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[111]),
        .I3(m_axi_rdata[111]),
        .O(s_axi_rdata[111]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[112]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[112]),
        .I3(m_axi_rdata[112]),
        .O(s_axi_rdata[112]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[113]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[113]),
        .I3(m_axi_rdata[113]),
        .O(s_axi_rdata[113]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[114]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[114]),
        .I3(m_axi_rdata[114]),
        .O(s_axi_rdata[114]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[115]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[115]),
        .I3(m_axi_rdata[115]),
        .O(s_axi_rdata[115]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[116]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[116]),
        .I3(m_axi_rdata[116]),
        .O(s_axi_rdata[116]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[117]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[117]),
        .I3(m_axi_rdata[117]),
        .O(s_axi_rdata[117]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[118]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[118]),
        .I3(m_axi_rdata[118]),
        .O(s_axi_rdata[118]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[119]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[119]),
        .I3(m_axi_rdata[119]),
        .O(s_axi_rdata[119]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[11]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[11]),
        .I3(m_axi_rdata[11]),
        .O(s_axi_rdata[11]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[120]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[120]),
        .I3(m_axi_rdata[120]),
        .O(s_axi_rdata[120]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[121]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[121]),
        .I3(m_axi_rdata[121]),
        .O(s_axi_rdata[121]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[122]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[122]),
        .I3(m_axi_rdata[122]),
        .O(s_axi_rdata[122]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[123]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[123]),
        .I3(m_axi_rdata[123]),
        .O(s_axi_rdata[123]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[124]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[124]),
        .I3(m_axi_rdata[124]),
        .O(s_axi_rdata[124]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[125]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[125]),
        .I3(m_axi_rdata[125]),
        .O(s_axi_rdata[125]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[126]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[126]),
        .I3(m_axi_rdata[126]),
        .O(s_axi_rdata[126]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[127]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[127]),
        .I3(m_axi_rdata[127]),
        .O(s_axi_rdata[127]));
  LUT5 #(
    .INIT(32'h718E8E71)) 
    \s_axi_rdata[127]_INST_0_i_1 
       (.I0(\current_word_1_reg[3] ),
        .I1(\USE_READ.rd_cmd_offset [3]),
        .I2(\s_axi_rdata[255]_INST_0_i_3_n_0 ),
        .I3(s_axi_rdata_0_sn_1),
        .I4(\USE_READ.rd_cmd_offset [4]),
        .O(\s_axi_rdata[127]_INST_0_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[128]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[0]),
        .I3(p_1_in[128]),
        .O(s_axi_rdata[128]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[129]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[1]),
        .I3(p_1_in[129]),
        .O(s_axi_rdata[129]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[12]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[12]),
        .I3(m_axi_rdata[12]),
        .O(s_axi_rdata[12]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[130]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[2]),
        .I3(p_1_in[130]),
        .O(s_axi_rdata[130]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[131]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[3]),
        .I3(p_1_in[131]),
        .O(s_axi_rdata[131]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[132]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[4]),
        .I3(p_1_in[132]),
        .O(s_axi_rdata[132]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[133]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[5]),
        .I3(p_1_in[133]),
        .O(s_axi_rdata[133]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[134]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[6]),
        .I3(p_1_in[134]),
        .O(s_axi_rdata[134]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[135]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[7]),
        .I3(p_1_in[135]),
        .O(s_axi_rdata[135]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[136]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[8]),
        .I3(p_1_in[136]),
        .O(s_axi_rdata[136]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[137]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[9]),
        .I3(p_1_in[137]),
        .O(s_axi_rdata[137]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[138]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[10]),
        .I3(p_1_in[138]),
        .O(s_axi_rdata[138]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[139]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[11]),
        .I3(p_1_in[139]),
        .O(s_axi_rdata[139]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[13]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[13]),
        .I3(m_axi_rdata[13]),
        .O(s_axi_rdata[13]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[140]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[12]),
        .I3(p_1_in[140]),
        .O(s_axi_rdata[140]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[141]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[13]),
        .I3(p_1_in[141]),
        .O(s_axi_rdata[141]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[142]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[14]),
        .I3(p_1_in[142]),
        .O(s_axi_rdata[142]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[143]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[15]),
        .I3(p_1_in[143]),
        .O(s_axi_rdata[143]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[144]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[16]),
        .I3(p_1_in[144]),
        .O(s_axi_rdata[144]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[145]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[17]),
        .I3(p_1_in[145]),
        .O(s_axi_rdata[145]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[146]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[18]),
        .I3(p_1_in[146]),
        .O(s_axi_rdata[146]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[147]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[19]),
        .I3(p_1_in[147]),
        .O(s_axi_rdata[147]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[148]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[20]),
        .I3(p_1_in[148]),
        .O(s_axi_rdata[148]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[149]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[21]),
        .I3(p_1_in[149]),
        .O(s_axi_rdata[149]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[14]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[14]),
        .I3(m_axi_rdata[14]),
        .O(s_axi_rdata[14]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[150]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[22]),
        .I3(p_1_in[150]),
        .O(s_axi_rdata[150]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[151]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[23]),
        .I3(p_1_in[151]),
        .O(s_axi_rdata[151]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[152]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[24]),
        .I3(p_1_in[152]),
        .O(s_axi_rdata[152]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[153]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[25]),
        .I3(p_1_in[153]),
        .O(s_axi_rdata[153]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[154]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[26]),
        .I3(p_1_in[154]),
        .O(s_axi_rdata[154]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[155]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[27]),
        .I3(p_1_in[155]),
        .O(s_axi_rdata[155]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[156]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[28]),
        .I3(p_1_in[156]),
        .O(s_axi_rdata[156]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[157]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[29]),
        .I3(p_1_in[157]),
        .O(s_axi_rdata[157]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[158]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[30]),
        .I3(p_1_in[158]),
        .O(s_axi_rdata[158]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[159]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[31]),
        .I3(p_1_in[159]),
        .O(s_axi_rdata[159]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[15]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[15]),
        .I3(m_axi_rdata[15]),
        .O(s_axi_rdata[15]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[160]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[32]),
        .I3(p_1_in[160]),
        .O(s_axi_rdata[160]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[161]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[33]),
        .I3(p_1_in[161]),
        .O(s_axi_rdata[161]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[162]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[34]),
        .I3(p_1_in[162]),
        .O(s_axi_rdata[162]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[163]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[35]),
        .I3(p_1_in[163]),
        .O(s_axi_rdata[163]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[164]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[36]),
        .I3(p_1_in[164]),
        .O(s_axi_rdata[164]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[165]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[37]),
        .I3(p_1_in[165]),
        .O(s_axi_rdata[165]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[166]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[38]),
        .I3(p_1_in[166]),
        .O(s_axi_rdata[166]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[167]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[39]),
        .I3(p_1_in[167]),
        .O(s_axi_rdata[167]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[168]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[40]),
        .I3(p_1_in[168]),
        .O(s_axi_rdata[168]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[169]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[41]),
        .I3(p_1_in[169]),
        .O(s_axi_rdata[169]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[16]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[16]),
        .I3(m_axi_rdata[16]),
        .O(s_axi_rdata[16]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[170]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[42]),
        .I3(p_1_in[170]),
        .O(s_axi_rdata[170]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[171]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[43]),
        .I3(p_1_in[171]),
        .O(s_axi_rdata[171]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[172]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[44]),
        .I3(p_1_in[172]),
        .O(s_axi_rdata[172]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[173]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[45]),
        .I3(p_1_in[173]),
        .O(s_axi_rdata[173]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[174]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[46]),
        .I3(p_1_in[174]),
        .O(s_axi_rdata[174]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[175]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[47]),
        .I3(p_1_in[175]),
        .O(s_axi_rdata[175]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[176]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[48]),
        .I3(p_1_in[176]),
        .O(s_axi_rdata[176]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[177]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[49]),
        .I3(p_1_in[177]),
        .O(s_axi_rdata[177]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[178]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[50]),
        .I3(p_1_in[178]),
        .O(s_axi_rdata[178]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[179]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[51]),
        .I3(p_1_in[179]),
        .O(s_axi_rdata[179]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[17]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[17]),
        .I3(m_axi_rdata[17]),
        .O(s_axi_rdata[17]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[180]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[52]),
        .I3(p_1_in[180]),
        .O(s_axi_rdata[180]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[181]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[53]),
        .I3(p_1_in[181]),
        .O(s_axi_rdata[181]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[182]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[54]),
        .I3(p_1_in[182]),
        .O(s_axi_rdata[182]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[183]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[55]),
        .I3(p_1_in[183]),
        .O(s_axi_rdata[183]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[184]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[56]),
        .I3(p_1_in[184]),
        .O(s_axi_rdata[184]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[185]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[57]),
        .I3(p_1_in[185]),
        .O(s_axi_rdata[185]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[186]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[58]),
        .I3(p_1_in[186]),
        .O(s_axi_rdata[186]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[187]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[59]),
        .I3(p_1_in[187]),
        .O(s_axi_rdata[187]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[188]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[60]),
        .I3(p_1_in[188]),
        .O(s_axi_rdata[188]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[189]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[61]),
        .I3(p_1_in[189]),
        .O(s_axi_rdata[189]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[18]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[18]),
        .I3(m_axi_rdata[18]),
        .O(s_axi_rdata[18]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[190]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[62]),
        .I3(p_1_in[190]),
        .O(s_axi_rdata[190]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[191]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[63]),
        .I3(p_1_in[191]),
        .O(s_axi_rdata[191]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[192]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[64]),
        .I3(p_1_in[192]),
        .O(s_axi_rdata[192]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[193]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[65]),
        .I3(p_1_in[193]),
        .O(s_axi_rdata[193]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[194]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[66]),
        .I3(p_1_in[194]),
        .O(s_axi_rdata[194]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[195]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[67]),
        .I3(p_1_in[195]),
        .O(s_axi_rdata[195]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[196]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[68]),
        .I3(p_1_in[196]),
        .O(s_axi_rdata[196]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[197]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[69]),
        .I3(p_1_in[197]),
        .O(s_axi_rdata[197]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[198]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[70]),
        .I3(p_1_in[198]),
        .O(s_axi_rdata[198]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[199]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[71]),
        .I3(p_1_in[199]),
        .O(s_axi_rdata[199]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[19]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[19]),
        .I3(m_axi_rdata[19]),
        .O(s_axi_rdata[19]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[1]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[1]),
        .I3(m_axi_rdata[1]),
        .O(s_axi_rdata[1]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[200]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[72]),
        .I3(p_1_in[200]),
        .O(s_axi_rdata[200]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[201]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[73]),
        .I3(p_1_in[201]),
        .O(s_axi_rdata[201]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[202]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[74]),
        .I3(p_1_in[202]),
        .O(s_axi_rdata[202]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[203]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[75]),
        .I3(p_1_in[203]),
        .O(s_axi_rdata[203]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[204]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[76]),
        .I3(p_1_in[204]),
        .O(s_axi_rdata[204]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[205]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[77]),
        .I3(p_1_in[205]),
        .O(s_axi_rdata[205]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[206]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[78]),
        .I3(p_1_in[206]),
        .O(s_axi_rdata[206]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[207]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[79]),
        .I3(p_1_in[207]),
        .O(s_axi_rdata[207]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[208]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[80]),
        .I3(p_1_in[208]),
        .O(s_axi_rdata[208]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[209]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[81]),
        .I3(p_1_in[209]),
        .O(s_axi_rdata[209]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[20]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[20]),
        .I3(m_axi_rdata[20]),
        .O(s_axi_rdata[20]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[210]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[82]),
        .I3(p_1_in[210]),
        .O(s_axi_rdata[210]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[211]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[83]),
        .I3(p_1_in[211]),
        .O(s_axi_rdata[211]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[212]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[84]),
        .I3(p_1_in[212]),
        .O(s_axi_rdata[212]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[213]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[85]),
        .I3(p_1_in[213]),
        .O(s_axi_rdata[213]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[214]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[86]),
        .I3(p_1_in[214]),
        .O(s_axi_rdata[214]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[215]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[87]),
        .I3(p_1_in[215]),
        .O(s_axi_rdata[215]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[216]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[88]),
        .I3(p_1_in[216]),
        .O(s_axi_rdata[216]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[217]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[89]),
        .I3(p_1_in[217]),
        .O(s_axi_rdata[217]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[218]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[90]),
        .I3(p_1_in[218]),
        .O(s_axi_rdata[218]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[219]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[91]),
        .I3(p_1_in[219]),
        .O(s_axi_rdata[219]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[21]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[21]),
        .I3(m_axi_rdata[21]),
        .O(s_axi_rdata[21]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[220]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[92]),
        .I3(p_1_in[220]),
        .O(s_axi_rdata[220]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[221]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[93]),
        .I3(p_1_in[221]),
        .O(s_axi_rdata[221]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[222]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[94]),
        .I3(p_1_in[222]),
        .O(s_axi_rdata[222]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[223]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[95]),
        .I3(p_1_in[223]),
        .O(s_axi_rdata[223]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[224]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[96]),
        .I3(p_1_in[224]),
        .O(s_axi_rdata[224]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[225]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[97]),
        .I3(p_1_in[225]),
        .O(s_axi_rdata[225]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[226]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[98]),
        .I3(p_1_in[226]),
        .O(s_axi_rdata[226]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[227]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[99]),
        .I3(p_1_in[227]),
        .O(s_axi_rdata[227]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[228]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[100]),
        .I3(p_1_in[228]),
        .O(s_axi_rdata[228]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[229]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[101]),
        .I3(p_1_in[229]),
        .O(s_axi_rdata[229]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[22]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[22]),
        .I3(m_axi_rdata[22]),
        .O(s_axi_rdata[22]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[230]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[102]),
        .I3(p_1_in[230]),
        .O(s_axi_rdata[230]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[231]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[103]),
        .I3(p_1_in[231]),
        .O(s_axi_rdata[231]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[232]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[104]),
        .I3(p_1_in[232]),
        .O(s_axi_rdata[232]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[233]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[105]),
        .I3(p_1_in[233]),
        .O(s_axi_rdata[233]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[234]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[106]),
        .I3(p_1_in[234]),
        .O(s_axi_rdata[234]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[235]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[107]),
        .I3(p_1_in[235]),
        .O(s_axi_rdata[235]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[236]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[108]),
        .I3(p_1_in[236]),
        .O(s_axi_rdata[236]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[237]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[109]),
        .I3(p_1_in[237]),
        .O(s_axi_rdata[237]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[238]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[110]),
        .I3(p_1_in[238]),
        .O(s_axi_rdata[238]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[239]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[111]),
        .I3(p_1_in[239]),
        .O(s_axi_rdata[239]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[23]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[23]),
        .I3(m_axi_rdata[23]),
        .O(s_axi_rdata[23]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[240]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[112]),
        .I3(p_1_in[240]),
        .O(s_axi_rdata[240]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[241]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[113]),
        .I3(p_1_in[241]),
        .O(s_axi_rdata[241]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[242]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[114]),
        .I3(p_1_in[242]),
        .O(s_axi_rdata[242]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[243]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[115]),
        .I3(p_1_in[243]),
        .O(s_axi_rdata[243]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[244]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[116]),
        .I3(p_1_in[244]),
        .O(s_axi_rdata[244]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[245]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[117]),
        .I3(p_1_in[245]),
        .O(s_axi_rdata[245]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[246]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[118]),
        .I3(p_1_in[246]),
        .O(s_axi_rdata[246]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[247]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[119]),
        .I3(p_1_in[247]),
        .O(s_axi_rdata[247]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[248]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[120]),
        .I3(p_1_in[248]),
        .O(s_axi_rdata[248]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[249]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[121]),
        .I3(p_1_in[249]),
        .O(s_axi_rdata[249]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[24]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[24]),
        .I3(m_axi_rdata[24]),
        .O(s_axi_rdata[24]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[250]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[122]),
        .I3(p_1_in[250]),
        .O(s_axi_rdata[250]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[251]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[123]),
        .I3(p_1_in[251]),
        .O(s_axi_rdata[251]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[252]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[124]),
        .I3(p_1_in[252]),
        .O(s_axi_rdata[252]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[253]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[125]),
        .I3(p_1_in[253]),
        .O(s_axi_rdata[253]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[254]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[126]),
        .I3(p_1_in[254]),
        .O(s_axi_rdata[254]));
  LUT4 #(
    .INIT(16'hF1E0)) 
    \s_axi_rdata[255]_INST_0 
       (.I0(dout[19]),
        .I1(\s_axi_rdata[255]_INST_0_i_1_n_0 ),
        .I2(m_axi_rdata[127]),
        .I3(p_1_in[255]),
        .O(s_axi_rdata[255]));
  LUT5 #(
    .INIT(32'h718E8E71)) 
    \s_axi_rdata[255]_INST_0_i_1 
       (.I0(\current_word_1_reg[3] ),
        .I1(\USE_READ.rd_cmd_offset [3]),
        .I2(\s_axi_rdata[255]_INST_0_i_3_n_0 ),
        .I3(s_axi_rdata_0_sn_1),
        .I4(\USE_READ.rd_cmd_offset [4]),
        .O(\s_axi_rdata[255]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000077F077FFFFF)) 
    \s_axi_rdata[255]_INST_0_i_3 
       (.I0(\USE_READ.rd_cmd_offset [0]),
        .I1(\current_word_1_reg[1] ),
        .I2(\USE_READ.rd_cmd_offset [1]),
        .I3(\current_word_1_reg[1]_0 ),
        .I4(\USE_READ.rd_cmd_offset [2]),
        .I5(\current_word_1_reg[2] ),
        .O(\s_axi_rdata[255]_INST_0_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[25]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[25]),
        .I3(m_axi_rdata[25]),
        .O(s_axi_rdata[25]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[26]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[26]),
        .I3(m_axi_rdata[26]),
        .O(s_axi_rdata[26]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[27]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[27]),
        .I3(m_axi_rdata[27]),
        .O(s_axi_rdata[27]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[28]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[28]),
        .I3(m_axi_rdata[28]),
        .O(s_axi_rdata[28]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[29]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[29]),
        .I3(m_axi_rdata[29]),
        .O(s_axi_rdata[29]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[2]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[2]),
        .I3(m_axi_rdata[2]),
        .O(s_axi_rdata[2]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[30]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[30]),
        .I3(m_axi_rdata[30]),
        .O(s_axi_rdata[30]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[31]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[31]),
        .I3(m_axi_rdata[31]),
        .O(s_axi_rdata[31]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[32]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[32]),
        .I3(m_axi_rdata[32]),
        .O(s_axi_rdata[32]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[33]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[33]),
        .I3(m_axi_rdata[33]),
        .O(s_axi_rdata[33]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[34]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[34]),
        .I3(m_axi_rdata[34]),
        .O(s_axi_rdata[34]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[35]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[35]),
        .I3(m_axi_rdata[35]),
        .O(s_axi_rdata[35]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[36]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[36]),
        .I3(m_axi_rdata[36]),
        .O(s_axi_rdata[36]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[37]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[37]),
        .I3(m_axi_rdata[37]),
        .O(s_axi_rdata[37]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[38]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[38]),
        .I3(m_axi_rdata[38]),
        .O(s_axi_rdata[38]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[39]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[39]),
        .I3(m_axi_rdata[39]),
        .O(s_axi_rdata[39]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[3]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[3]),
        .I3(m_axi_rdata[3]),
        .O(s_axi_rdata[3]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[40]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[40]),
        .I3(m_axi_rdata[40]),
        .O(s_axi_rdata[40]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[41]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[41]),
        .I3(m_axi_rdata[41]),
        .O(s_axi_rdata[41]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[42]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[42]),
        .I3(m_axi_rdata[42]),
        .O(s_axi_rdata[42]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[43]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[43]),
        .I3(m_axi_rdata[43]),
        .O(s_axi_rdata[43]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[44]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[44]),
        .I3(m_axi_rdata[44]),
        .O(s_axi_rdata[44]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[45]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[45]),
        .I3(m_axi_rdata[45]),
        .O(s_axi_rdata[45]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[46]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[46]),
        .I3(m_axi_rdata[46]),
        .O(s_axi_rdata[46]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[47]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[47]),
        .I3(m_axi_rdata[47]),
        .O(s_axi_rdata[47]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[48]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[48]),
        .I3(m_axi_rdata[48]),
        .O(s_axi_rdata[48]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[49]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[49]),
        .I3(m_axi_rdata[49]),
        .O(s_axi_rdata[49]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[4]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[4]),
        .I3(m_axi_rdata[4]),
        .O(s_axi_rdata[4]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[50]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[50]),
        .I3(m_axi_rdata[50]),
        .O(s_axi_rdata[50]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[51]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[51]),
        .I3(m_axi_rdata[51]),
        .O(s_axi_rdata[51]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[52]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[52]),
        .I3(m_axi_rdata[52]),
        .O(s_axi_rdata[52]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[53]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[53]),
        .I3(m_axi_rdata[53]),
        .O(s_axi_rdata[53]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[54]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[54]),
        .I3(m_axi_rdata[54]),
        .O(s_axi_rdata[54]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[55]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[55]),
        .I3(m_axi_rdata[55]),
        .O(s_axi_rdata[55]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[56]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[56]),
        .I3(m_axi_rdata[56]),
        .O(s_axi_rdata[56]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[57]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[57]),
        .I3(m_axi_rdata[57]),
        .O(s_axi_rdata[57]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[58]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[58]),
        .I3(m_axi_rdata[58]),
        .O(s_axi_rdata[58]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[59]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[59]),
        .I3(m_axi_rdata[59]),
        .O(s_axi_rdata[59]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[5]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[5]),
        .I3(m_axi_rdata[5]),
        .O(s_axi_rdata[5]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[60]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[60]),
        .I3(m_axi_rdata[60]),
        .O(s_axi_rdata[60]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[61]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[61]),
        .I3(m_axi_rdata[61]),
        .O(s_axi_rdata[61]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[62]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[62]),
        .I3(m_axi_rdata[62]),
        .O(s_axi_rdata[62]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[63]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[63]),
        .I3(m_axi_rdata[63]),
        .O(s_axi_rdata[63]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[64]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[64]),
        .I3(m_axi_rdata[64]),
        .O(s_axi_rdata[64]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[65]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[65]),
        .I3(m_axi_rdata[65]),
        .O(s_axi_rdata[65]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[66]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[66]),
        .I3(m_axi_rdata[66]),
        .O(s_axi_rdata[66]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[67]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[67]),
        .I3(m_axi_rdata[67]),
        .O(s_axi_rdata[67]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[68]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[68]),
        .I3(m_axi_rdata[68]),
        .O(s_axi_rdata[68]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[69]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[69]),
        .I3(m_axi_rdata[69]),
        .O(s_axi_rdata[69]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[6]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[6]),
        .I3(m_axi_rdata[6]),
        .O(s_axi_rdata[6]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[70]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[70]),
        .I3(m_axi_rdata[70]),
        .O(s_axi_rdata[70]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[71]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[71]),
        .I3(m_axi_rdata[71]),
        .O(s_axi_rdata[71]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[72]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[72]),
        .I3(m_axi_rdata[72]),
        .O(s_axi_rdata[72]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[73]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[73]),
        .I3(m_axi_rdata[73]),
        .O(s_axi_rdata[73]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[74]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[74]),
        .I3(m_axi_rdata[74]),
        .O(s_axi_rdata[74]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[75]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[75]),
        .I3(m_axi_rdata[75]),
        .O(s_axi_rdata[75]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[76]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[76]),
        .I3(m_axi_rdata[76]),
        .O(s_axi_rdata[76]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[77]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[77]),
        .I3(m_axi_rdata[77]),
        .O(s_axi_rdata[77]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[78]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[78]),
        .I3(m_axi_rdata[78]),
        .O(s_axi_rdata[78]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[79]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[79]),
        .I3(m_axi_rdata[79]),
        .O(s_axi_rdata[79]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[7]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[7]),
        .I3(m_axi_rdata[7]),
        .O(s_axi_rdata[7]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[80]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[80]),
        .I3(m_axi_rdata[80]),
        .O(s_axi_rdata[80]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[81]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[81]),
        .I3(m_axi_rdata[81]),
        .O(s_axi_rdata[81]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[82]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[82]),
        .I3(m_axi_rdata[82]),
        .O(s_axi_rdata[82]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[83]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[83]),
        .I3(m_axi_rdata[83]),
        .O(s_axi_rdata[83]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[84]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[84]),
        .I3(m_axi_rdata[84]),
        .O(s_axi_rdata[84]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[85]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[85]),
        .I3(m_axi_rdata[85]),
        .O(s_axi_rdata[85]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[86]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[86]),
        .I3(m_axi_rdata[86]),
        .O(s_axi_rdata[86]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[87]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[87]),
        .I3(m_axi_rdata[87]),
        .O(s_axi_rdata[87]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[88]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[88]),
        .I3(m_axi_rdata[88]),
        .O(s_axi_rdata[88]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[89]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[89]),
        .I3(m_axi_rdata[89]),
        .O(s_axi_rdata[89]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[8]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[8]),
        .I3(m_axi_rdata[8]),
        .O(s_axi_rdata[8]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[90]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[90]),
        .I3(m_axi_rdata[90]),
        .O(s_axi_rdata[90]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[91]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[91]),
        .I3(m_axi_rdata[91]),
        .O(s_axi_rdata[91]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[92]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[92]),
        .I3(m_axi_rdata[92]),
        .O(s_axi_rdata[92]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[93]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[93]),
        .I3(m_axi_rdata[93]),
        .O(s_axi_rdata[93]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[94]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[94]),
        .I3(m_axi_rdata[94]),
        .O(s_axi_rdata[94]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[95]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[95]),
        .I3(m_axi_rdata[95]),
        .O(s_axi_rdata[95]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[96]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[96]),
        .I3(m_axi_rdata[96]),
        .O(s_axi_rdata[96]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[97]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[97]),
        .I3(m_axi_rdata[97]),
        .O(s_axi_rdata[97]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[98]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[98]),
        .I3(m_axi_rdata[98]),
        .O(s_axi_rdata[98]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[99]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[99]),
        .I3(m_axi_rdata[99]),
        .O(s_axi_rdata[99]));
  LUT4 #(
    .INIT(16'hFD20)) 
    \s_axi_rdata[9]_INST_0 
       (.I0(\s_axi_rdata[127]_INST_0_i_1_n_0 ),
        .I1(dout[19]),
        .I2(p_1_in[9]),
        .I3(m_axi_rdata[9]),
        .O(s_axi_rdata[9]));
  LUT2 #(
    .INIT(4'h2)) 
    s_axi_rlast_INST_0
       (.I0(m_axi_rlast),
        .I1(\USE_READ.rd_cmd_split ),
        .O(s_axi_rlast));
  LUT6 #(
    .INIT(64'h00000000AAEF0000)) 
    s_axi_rvalid_INST_0
       (.I0(s_axi_rvalid_INST_0_i_1_n_0),
        .I1(\goreg_dm.dout_i_reg[2] ),
        .I2(\goreg_dm.dout_i_reg[18] ),
        .I3(s_axi_rvalid_INST_0_i_4_n_0),
        .I4(m_axi_rvalid),
        .I5(empty),
        .O(s_axi_rvalid));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4700)) 
    s_axi_rvalid_INST_0_i_1
       (.I0(dout[10]),
        .I1(first_mi_word),
        .I2(s_axi_rvalid_0),
        .I3(s_axi_rvalid_1),
        .I4(dout[19]),
        .I5(dout[20]),
        .O(s_axi_rvalid_INST_0_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'h57)) 
    s_axi_rvalid_INST_0_i_2
       (.I0(dout[2]),
        .I1(dout[1]),
        .I2(dout[0]),
        .O(\goreg_dm.dout_i_reg[2] ));
  LUT2 #(
    .INIT(4'h2)) 
    s_axi_rvalid_INST_0_i_3
       (.I0(\USE_READ.rd_cmd_mask [4]),
        .I1(\current_word_1_reg[4] ),
        .O(\goreg_dm.dout_i_reg[18] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEEC0EE00)) 
    s_axi_rvalid_INST_0_i_4
       (.I0(p_0_in[3]),
        .I1(p_0_in[2]),
        .I2(dout[0]),
        .I3(dout[2]),
        .I4(dout[1]),
        .I5(s_axi_rvalid_INST_0_i_7_n_0),
        .O(s_axi_rvalid_INST_0_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'hFFFCA8A8)) 
    s_axi_rvalid_INST_0_i_7
       (.I0(p_0_in[1]),
        .I1(dout[1]),
        .I2(dout[2]),
        .I3(dout[0]),
        .I4(p_0_in[0]),
        .O(s_axi_rvalid_INST_0_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h8)) 
    split_ongoing_i_1__0
       (.I0(m_axi_arready),
        .I1(command_ongoing_reg),
        .O(m_axi_arready_2));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_26_fifo_gen" *) 
module axi4_dwtrans_axi_data_fifo_v2_1_26_fifo_gen__parameterized0__xdcDup__1
   (dout,
    \S_AXI_ASIZE_Q_reg[2] ,
    E,
    D,
    s_axi_awvalid_0,
    command_ongoing_reg,
    cmd_b_push_block_reg,
    cmd_b_push_block_reg_0,
    cmd_b_push_block_reg_1,
    cmd_push_block_reg,
    m_axi_awready_0,
    wr_en,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    m_axi_wvalid,
    s_axi_wready,
    s_axi_wvalid_0,
    \goreg_dm.dout_i_reg[18] ,
    \areset_d_reg[0] ,
    CLK,
    SR,
    din,
    Q,
    fix_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_6_0 ,
    access_is_wrap_q,
    split_ongoing,
    first_mi_word,
    \current_word_1_reg[3] ,
    s_axi_awvalid,
    S_AXI_AREADY_I_reg,
    S_AXI_AREADY_I_reg_0,
    S_AXI_AREADY_I_reg_1,
    command_ongoing,
    m_axi_awready,
    command_ongoing_reg_0,
    cmd_b_push_block,
    out,
    \USE_WRITE.wr_cmd_b_ready ,
    \USE_B_CHANNEL.cmd_b_empty_i_reg ,
    cmd_b_empty,
    cmd_push_block,
    full,
    m_axi_awvalid_INST_0_i_1_0,
    s_axi_bid,
    access_is_fix_q,
    \m_axi_awlen[7] ,
    \m_axi_awlen[7]_0 ,
    \m_axi_awlen[7]_INST_0_i_6_1 ,
    wrap_need_to_split_q,
    \m_axi_awlen[2] ,
    incr_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_5_0 ,
    access_is_incr_q,
    \m_axi_awlen[7]_INST_0_i_5_1 ,
    \gpr1.dout_i_reg[29] ,
    si_full_size_q,
    \gpr1.dout_i_reg[15] ,
    \gpr1.dout_i_reg[15]_0 ,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \gpr1.dout_i_reg[15]_4 ,
    \m_axi_awlen[2]_INST_0_i_3_0 ,
    legal_wrap_len_q,
    s_axi_wvalid,
    m_axi_wready,
    s_axi_wready_0,
    \current_word_1_reg[4] ,
    \current_word_1_reg[4]_0 ,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1[4]_i_2_0 );
  output [18:0]dout;
  output [10:0]\S_AXI_ASIZE_Q_reg[2] ;
  output [0:0]E;
  output [4:0]D;
  output s_axi_awvalid_0;
  output command_ongoing_reg;
  output cmd_b_push_block_reg;
  output [0:0]cmd_b_push_block_reg_0;
  output cmd_b_push_block_reg_1;
  output cmd_push_block_reg;
  output [0:0]m_axi_awready_0;
  output wr_en;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]s_axi_wvalid_0;
  output [4:0]\goreg_dm.dout_i_reg[18] ;
  output \areset_d_reg[0] ;
  input CLK;
  input [0:0]SR;
  input [9:0]din;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  input access_is_wrap_q;
  input split_ongoing;
  input first_mi_word;
  input [1:0]\current_word_1_reg[3] ;
  input s_axi_awvalid;
  input [0:0]S_AXI_AREADY_I_reg;
  input S_AXI_AREADY_I_reg_0;
  input S_AXI_AREADY_I_reg_1;
  input command_ongoing;
  input m_axi_awready;
  input command_ongoing_reg_0;
  input cmd_b_push_block;
  input out;
  input \USE_WRITE.wr_cmd_b_ready ;
  input \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  input cmd_b_empty;
  input cmd_push_block;
  input full;
  input [3:0]m_axi_awvalid_INST_0_i_1_0;
  input [3:0]s_axi_bid;
  input access_is_fix_q;
  input [7:0]\m_axi_awlen[7] ;
  input [7:0]\m_axi_awlen[7]_0 ;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6_1 ;
  input wrap_need_to_split_q;
  input [2:0]\m_axi_awlen[2] ;
  input incr_need_to_split_q;
  input \m_axi_awlen[7]_INST_0_i_5_0 ;
  input access_is_incr_q;
  input \m_axi_awlen[7]_INST_0_i_5_1 ;
  input \gpr1.dout_i_reg[29] ;
  input si_full_size_q;
  input [0:0]\gpr1.dout_i_reg[15] ;
  input [4:0]\gpr1.dout_i_reg[15]_0 ;
  input \gpr1.dout_i_reg[15]_1 ;
  input \gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input \gpr1.dout_i_reg[15]_4 ;
  input [2:0]\m_axi_awlen[2]_INST_0_i_3_0 ;
  input legal_wrap_len_q;
  input s_axi_wvalid;
  input m_axi_wready;
  input s_axi_wready_0;
  input \current_word_1_reg[4] ;
  input \current_word_1_reg[4]_0 ;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1[4]_i_2_0 ;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire S_AXI_AREADY_I_i_3_n_0;
  wire [0:0]S_AXI_AREADY_I_reg;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire [10:0]\S_AXI_ASIZE_Q_reg[2] ;
  wire \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ;
  wire \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire [4:0]\USE_WRITE.wr_cmd_mask ;
  wire \USE_WRITE.wr_cmd_mirror ;
  wire \USE_WRITE.wr_cmd_ready ;
  wire [2:0]\USE_WRITE.wr_cmd_size ;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire \areset_d_reg[0] ;
  wire cmd_b_empty;
  wire cmd_b_empty0;
  wire cmd_b_push_block;
  wire cmd_b_push_block_reg;
  wire [0:0]cmd_b_push_block_reg_0;
  wire cmd_b_push_block_reg_1;
  wire cmd_push_block;
  wire cmd_push_block_reg;
  wire [2:0]cmd_size_ii;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire command_ongoing_reg_0;
  wire \current_word_1[2]_i_2__0_n_0 ;
  wire \current_word_1[2]_i_3__0_n_0 ;
  wire \current_word_1[3]_i_2__0_n_0 ;
  wire \current_word_1[4]_i_2_0 ;
  wire \current_word_1[4]_i_2_n_0 ;
  wire \current_word_1[4]_i_3_n_0 ;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire [1:0]\current_word_1_reg[3] ;
  wire \current_word_1_reg[4] ;
  wire \current_word_1_reg[4]_0 ;
  wire [9:0]din;
  wire [18:0]dout;
  wire empty;
  wire fifo_gen_inst_i_13_n_0;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire full;
  wire full_0;
  wire [4:0]\goreg_dm.dout_i_reg[18] ;
  wire [0:0]\gpr1.dout_i_reg[15] ;
  wire [4:0]\gpr1.dout_i_reg[15]_0 ;
  wire \gpr1.dout_i_reg[15]_1 ;
  wire \gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire \gpr1.dout_i_reg[15]_4 ;
  wire \gpr1.dout_i_reg[29] ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire \m_axi_awlen[0]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_5_n_0 ;
  wire [2:0]\m_axi_awlen[2] ;
  wire \m_axi_awlen[2]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[2]_INST_0_i_2_n_0 ;
  wire [2:0]\m_axi_awlen[2]_INST_0_i_3_0 ;
  wire \m_axi_awlen[2]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[2]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_5_n_0 ;
  wire \m_axi_awlen[4]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[4]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[4]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[6]_INST_0_i_1_n_0 ;
  wire [7:0]\m_axi_awlen[7] ;
  wire [7:0]\m_axi_awlen[7]_0 ;
  wire \m_axi_awlen[7]_INST_0_i_10_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_11_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_14_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_5_0 ;
  wire \m_axi_awlen[7]_INST_0_i_5_1 ;
  wire \m_axi_awlen[7]_INST_0_i_5_n_0 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6_1 ;
  wire \m_axi_awlen[7]_INST_0_i_6_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_7_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_8_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_9_n_0 ;
  wire m_axi_awready;
  wire [0:0]m_axi_awready_0;
  wire [3:0]m_axi_awvalid_INST_0_i_1_0;
  wire m_axi_awvalid_INST_0_i_1_n_0;
  wire m_axi_awvalid_INST_0_i_2_n_0;
  wire m_axi_wready;
  wire m_axi_wvalid;
  wire out;
  wire [31:19]p_0_out;
  wire s_axi_awvalid;
  wire s_axi_awvalid_0;
  wire [3:0]s_axi_bid;
  wire s_axi_wready;
  wire s_axi_wready_0;
  wire s_axi_wready_INST_0_i_1_n_0;
  wire s_axi_wready_INST_0_i_2_n_0;
  wire s_axi_wvalid;
  wire [0:0]s_axi_wvalid_0;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wr_en;
  wire wrap_need_to_split_q;
  wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_almost_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED;
  wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_valid_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED;
  wire [30:30]NLW_fifo_gen_inst_dout_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED;

  LUT5 #(
    .INIT(32'h44F4FFF4)) 
    S_AXI_AREADY_I_i_2
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(S_AXI_AREADY_I_reg_1),
        .I2(S_AXI_AREADY_I_i_3_n_0),
        .I3(S_AXI_AREADY_I_reg),
        .I4(s_axi_awvalid),
        .O(\areset_d_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'h08)) 
    S_AXI_AREADY_I_i_3
       (.I0(m_axi_awready),
        .I1(command_ongoing_reg),
        .I2(command_ongoing_reg_0),
        .O(S_AXI_AREADY_I_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \USE_B_CHANNEL.cmd_b_depth[1]_i_1 
       (.I0(Q[0]),
        .I1(cmd_b_empty0),
        .I2(Q[1]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT4 #(
    .INIT(16'h78E1)) 
    \USE_B_CHANNEL.cmd_b_depth[2]_i_1 
       (.I0(cmd_b_empty0),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT5 #(
    .INIT(32'h7FFE8001)) 
    \USE_B_CHANNEL.cmd_b_depth[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(cmd_b_empty0),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \USE_B_CHANNEL.cmd_b_depth[4]_i_1 
       (.I0(Q[4]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(cmd_b_empty0),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \USE_B_CHANNEL.cmd_b_depth[4]_i_2 
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(\USE_WRITE.wr_cmd_b_ready ),
        .O(cmd_b_empty0));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \USE_B_CHANNEL.cmd_b_depth[5]_i_1 
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(\USE_WRITE.wr_cmd_b_ready ),
        .O(cmd_b_push_block_reg_0));
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \USE_B_CHANNEL.cmd_b_depth[5]_i_2 
       (.I0(Q[5]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT4 #(
    .INIT(16'h80FE)) 
    \USE_B_CHANNEL.cmd_b_depth[5]_i_3 
       (.I0(cmd_b_empty0),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .O(\USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT5 #(
    .INIT(32'hF2DDD000)) 
    \USE_B_CHANNEL.cmd_b_empty_i_i_1 
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(\USE_B_CHANNEL.cmd_b_empty_i_reg ),
        .I3(\USE_WRITE.wr_cmd_b_ready ),
        .I4(cmd_b_empty),
        .O(cmd_b_push_block_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'h00E0)) 
    cmd_b_push_block_i_1
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(out),
        .I3(S_AXI_AREADY_I_reg),
        .O(cmd_b_push_block_reg));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'h4E00)) 
    cmd_push_block_i_1
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .I2(m_axi_awready),
        .I3(out),
        .O(cmd_push_block_reg));
  LUT6 #(
    .INIT(64'h8FFF8F8F88008888)) 
    command_ongoing_i_1
       (.I0(s_axi_awvalid),
        .I1(S_AXI_AREADY_I_reg),
        .I2(S_AXI_AREADY_I_i_3_n_0),
        .I3(S_AXI_AREADY_I_reg_0),
        .I4(S_AXI_AREADY_I_reg_1),
        .I5(command_ongoing),
        .O(s_axi_awvalid_0));
  LUT5 #(
    .INIT(32'h22222228)) 
    \current_word_1[0]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [0]),
        .I1(\current_word_1_reg[1]_0 ),
        .I2(cmd_size_ii[1]),
        .I3(cmd_size_ii[2]),
        .I4(cmd_size_ii[0]),
        .O(\goreg_dm.dout_i_reg[18] [0]));
  LUT6 #(
    .INIT(64'h8888828888888282)) 
    \current_word_1[1]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [1]),
        .I1(\current_word_1_reg[1] ),
        .I2(cmd_size_ii[2]),
        .I3(cmd_size_ii[0]),
        .I4(cmd_size_ii[1]),
        .I5(\current_word_1_reg[1]_0 ),
        .O(\goreg_dm.dout_i_reg[18] [1]));
  LUT5 #(
    .INIT(32'h88828888)) 
    \current_word_1[2]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [2]),
        .I1(\current_word_1[2]_i_2__0_n_0 ),
        .I2(cmd_size_ii[2]),
        .I3(cmd_size_ii[0]),
        .I4(cmd_size_ii[1]),
        .O(\goreg_dm.dout_i_reg[18] [2]));
  LUT5 #(
    .INIT(32'h6665666A)) 
    \current_word_1[2]_i_2__0 
       (.I0(\current_word_1[2]_i_3__0_n_0 ),
        .I1(dout[15]),
        .I2(first_mi_word),
        .I3(dout[18]),
        .I4(\current_word_1_reg[3] [0]),
        .O(\current_word_1[2]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h02030000)) 
    \current_word_1[2]_i_3__0 
       (.I0(cmd_size_ii[0]),
        .I1(cmd_size_ii[2]),
        .I2(cmd_size_ii[1]),
        .I3(\current_word_1_reg[1]_0 ),
        .I4(\current_word_1_reg[1] ),
        .O(\current_word_1[2]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h88882888)) 
    \current_word_1[3]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [3]),
        .I1(\current_word_1[3]_i_2__0_n_0 ),
        .I2(cmd_size_ii[1]),
        .I3(cmd_size_ii[0]),
        .I4(cmd_size_ii[2]),
        .O(\goreg_dm.dout_i_reg[18] [3]));
  LUT5 #(
    .INIT(32'h999A9995)) 
    \current_word_1[3]_i_2__0 
       (.I0(\current_word_1[4]_i_3_n_0 ),
        .I1(dout[16]),
        .I2(first_mi_word),
        .I3(dout[18]),
        .I4(\current_word_1_reg[3] [1]),
        .O(\current_word_1[3]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \current_word_1[4]_i_1 
       (.I0(\USE_WRITE.wr_cmd_mask [4]),
        .I1(\current_word_1[4]_i_2_n_0 ),
        .O(\goreg_dm.dout_i_reg[18] [4]));
  LUT6 #(
    .INIT(64'h599A59595959A659)) 
    \current_word_1[4]_i_2 
       (.I0(\current_word_1_reg[4] ),
        .I1(\current_word_1_reg[4]_0 ),
        .I2(\current_word_1[4]_i_3_n_0 ),
        .I3(cmd_size_ii[2]),
        .I4(cmd_size_ii[0]),
        .I5(cmd_size_ii[1]),
        .O(\current_word_1[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEBEFEAEFFFFFFFFF)) 
    \current_word_1[4]_i_3 
       (.I0(cmd_size_ii[2]),
        .I1(cmd_size_ii[0]),
        .I2(cmd_size_ii[1]),
        .I3(\current_word_1_reg[1] ),
        .I4(\current_word_1_reg[1]_0 ),
        .I5(\current_word_1[4]_i_2_0 ),
        .O(\current_word_1[4]_i_3_n_0 ));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "4" *) 
  (* C_AXIS_TID_WIDTH = "8" *) 
  (* C_AXIS_TKEEP_WIDTH = "4" *) 
  (* C_AXIS_TSTRB_WIDTH = "4" *) 
  (* C_AXIS_TUSER_WIDTH = "4" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "2" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "0" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "6" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "32" *) 
  (* C_DIN_WIDTH_AXIS = "1" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "32" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_FULL_FLAGS_RST_VAL = "0" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "0" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "0" *) 
  (* C_HAS_AXIS_TLAST = "0" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "0" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "0" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "0" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_MEMORY_TYPE = "2" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "0" *) 
  (* C_PRELOAD_REGS = "1" *) 
  (* C_PRIM_FIFO_TYPE = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "0" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "6" *) 
  (* C_RD_DEPTH = "32" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "5" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "1" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "6" *) 
  (* C_WR_DEPTH = "32" *) 
  (* C_WR_DEPTH_AXIS = "1024" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "5" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "10" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* is_du_within_envelope = "true" *) 
  axi4_dwtrans_fifo_generator_v13_2_7__parameterized0__xdcDup__1 fifo_gen_inst
       (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]),
        .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]),
        .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(CLK),
        .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]),
        .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED),
        .din({p_0_out[31],din[9:8],p_0_out[28:19],din[7:3],\S_AXI_ASIZE_Q_reg[2] ,din[2:0]}),
        .dout({dout[18],NLW_fifo_gen_inst_dout_UNCONNECTED[30],\USE_WRITE.wr_cmd_mirror ,dout[17:8],\USE_WRITE.wr_cmd_mask ,cmd_size_ii,dout[7:0],\USE_WRITE.wr_cmd_size }),
        .empty(empty),
        .full(full_0),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]),
        .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]),
        .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]),
        .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]),
        .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]),
        .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]),
        .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]),
        .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]),
        .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]),
        .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED),
        .m_axis_tready(1'b0),
        .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]),
        .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]),
        .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED),
        .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]),
        .rd_en(\USE_WRITE.wr_cmd_ready ),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED),
        .rst(SR),
        .s_aclk(1'b0),
        .s_aclk_en(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock({1'b0,1'b0}),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock({1'b0,1'b0}),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(1'b0),
        .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tvalid(1'b0),
        .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED),
        .valid(NLW_fifo_gen_inst_valid_UNCONNECTED),
        .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]),
        .wr_en(E),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED));
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_1
       (.I0(access_is_fix_q),
        .I1(din[8]),
        .O(p_0_out[31]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_10
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_2 ),
        .I3(\gpr1.dout_i_reg[15]_0 [1]),
        .I4(access_is_wrap_q_reg),
        .I5(din[4]),
        .O(p_0_out[20]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_11
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_1 ),
        .I3(\gpr1.dout_i_reg[15]_0 [0]),
        .I4(access_is_wrap_q_reg),
        .I5(din[3]),
        .O(p_0_out[19]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    fifo_gen_inst_i_12
       (.I0(m_axi_wready),
        .I1(empty),
        .I2(s_axi_wvalid),
        .I3(s_axi_wready_0),
        .O(\USE_WRITE.wr_cmd_ready ));
  LUT6 #(
    .INIT(64'h0040CCCC4444CCCC)) 
    fifo_gen_inst_i_13
       (.I0(access_is_wrap_q),
        .I1(\gpr1.dout_i_reg[15]_0 [4]),
        .I2(\gpr1.dout_i_reg[15] ),
        .I3(si_full_size_q),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(fifo_gen_inst_i_13_n_0));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_14
       (.I0(split_ongoing),
        .I1(access_is_incr_q),
        .O(split_ongoing_reg));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_15
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .O(access_is_wrap_q_reg));
  LUT3 #(
    .INIT(8'h80)) 
    fifo_gen_inst_i_2
       (.I0(fifo_gen_inst_i_13_n_0),
        .I1(din[7]),
        .I2(\gpr1.dout_i_reg[29] ),
        .O(p_0_out[28]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_3
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [3]),
        .I3(access_is_wrap_q_reg),
        .I4(din[6]),
        .I5(\gpr1.dout_i_reg[15]_4 ),
        .O(p_0_out[27]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_4
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [2]),
        .I3(access_is_wrap_q_reg),
        .I4(din[5]),
        .I5(\gpr1.dout_i_reg[15]_3 ),
        .O(p_0_out[26]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_5
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [1]),
        .I3(access_is_wrap_q_reg),
        .I4(din[4]),
        .I5(\gpr1.dout_i_reg[15]_2 ),
        .O(p_0_out[25]));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT2 #(
    .INIT(4'h2)) 
    fifo_gen_inst_i_6
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .O(wr_en));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_6__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [0]),
        .I3(access_is_wrap_q_reg),
        .I4(din[3]),
        .I5(\gpr1.dout_i_reg[15]_1 ),
        .O(p_0_out[24]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_7__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15] ),
        .I3(\gpr1.dout_i_reg[15]_0 [4]),
        .I4(access_is_wrap_q_reg),
        .I5(din[7]),
        .O(p_0_out[23]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_8__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_4 ),
        .I3(\gpr1.dout_i_reg[15]_0 [3]),
        .I4(access_is_wrap_q_reg),
        .I5(din[6]),
        .O(p_0_out[22]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_9
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_3 ),
        .I3(\gpr1.dout_i_reg[15]_0 [2]),
        .I4(access_is_wrap_q_reg),
        .I5(din[5]),
        .O(p_0_out[21]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'h20)) 
    first_word_i_1
       (.I0(s_axi_wvalid),
        .I1(empty),
        .I2(m_axi_wready),
        .O(s_axi_wvalid_0));
  LUT6 #(
    .INIT(64'hF704F7F708FB0808)) 
    \m_axi_awlen[0]_INST_0 
       (.I0(\m_axi_awlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[2] [0]),
        .I5(\m_axi_awlen[0]_INST_0_i_1_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[0]_INST_0_i_1 
       (.I0(\m_axi_awlen[7]_0 [0]),
        .I1(din[8]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [0]),
        .I3(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_awlen[1]_INST_0_i_3_n_0 ),
        .O(\m_axi_awlen[0]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0BFBF404F4040BFB)) 
    \m_axi_awlen[1]_INST_0 
       (.I0(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .I1(\m_axi_awlen[2] [1]),
        .I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[7] [1]),
        .I4(\m_axi_awlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_awlen[1]_INST_0_i_2_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [1]));
  LUT6 #(
    .INIT(64'h00000000001DFF1D)) 
    \m_axi_awlen[1]_INST_0_i_1 
       (.I0(\m_axi_awlen[1]_INST_0_i_3_n_0 ),
        .I1(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [0]),
        .I3(din[8]),
        .I4(\m_axi_awlen[7]_0 [0]),
        .I5(\m_axi_awlen[1]_INST_0_i_4_n_0 ),
        .O(\m_axi_awlen[1]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h47444777)) 
    \m_axi_awlen[1]_INST_0_i_2 
       (.I0(\m_axi_awlen[7]_0 [1]),
        .I1(din[8]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [1]),
        .I3(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_awlen[1]_INST_0_i_5_n_0 ),
        .O(\m_axi_awlen[1]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[1]_INST_0_i_3 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [0]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[2]_INST_0_i_3_0 [0]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[1]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hF704F7F7)) 
    \m_axi_awlen[1]_INST_0_i_4 
       (.I0(\m_axi_awlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[2] [0]),
        .O(\m_axi_awlen[1]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[1]_INST_0_i_5 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [1]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[2]_INST_0_i_3_0 [1]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[1]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_awlen[2]_INST_0 
       (.I0(\m_axi_awlen[2]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7] [2]),
        .I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[2] [2]),
        .I4(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .I5(\m_axi_awlen[2]_INST_0_i_3_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [2]));
  LUT6 #(
    .INIT(64'hFFFF88B888B80000)) 
    \m_axi_awlen[2]_INST_0_i_1 
       (.I0(\m_axi_awlen[7] [1]),
        .I1(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I2(\m_axi_awlen[2] [1]),
        .I3(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_awlen[1]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[2]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT5 #(
    .INIT(32'h0000FD0D)) 
    \m_axi_awlen[2]_INST_0_i_2 
       (.I0(access_is_incr_q),
        .I1(din[8]),
        .I2(incr_need_to_split_q),
        .I3(split_ongoing),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[2]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_awlen[2]_INST_0_i_3 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_1 [2]),
        .I1(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I2(\m_axi_awlen[2]_INST_0_i_4_n_0 ),
        .I3(\m_axi_awlen[7]_0 [2]),
        .I4(din[8]),
        .O(\m_axi_awlen[2]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[2]_INST_0_i_4 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [2]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[2]_INST_0_i_3_0 [2]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[2]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_awlen[3]_INST_0 
       (.I0(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7] [3]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_awlen[3]_INST_0_i_2_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [3]));
  LUT5 #(
    .INIT(32'hBBB2B222)) 
    \m_axi_awlen[3]_INST_0_i_1 
       (.I0(\m_axi_awlen[3]_INST_0_i_3_n_0 ),
        .I1(\m_axi_awlen[2]_INST_0_i_3_n_0 ),
        .I2(\m_axi_awlen[1]_INST_0_i_2_n_0 ),
        .I3(\m_axi_awlen[1]_INST_0_i_1_n_0 ),
        .I4(\m_axi_awlen[3]_INST_0_i_4_n_0 ),
        .O(\m_axi_awlen[3]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[3]_INST_0_i_2 
       (.I0(\m_axi_awlen[7]_0 [3]),
        .I1(din[8]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [3]),
        .I3(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_awlen[3]_INST_0_i_5_n_0 ),
        .O(\m_axi_awlen[3]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_awlen[3]_INST_0_i_3 
       (.I0(\m_axi_awlen[7] [2]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[2] [2]),
        .I4(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[3]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_awlen[3]_INST_0_i_4 
       (.I0(\m_axi_awlen[7] [1]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[2] [1]),
        .I4(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[3]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_awlen[3]_INST_0_i_5 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_awlen[7]_INST_0_i_6_0 [3]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_awlen[3]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_awlen[4]_INST_0 
       (.I0(\m_axi_awlen[4]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7] [4]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [4]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT5 #(
    .INIT(32'h2000FF20)) 
    \m_axi_awlen[4]_INST_0_i_1 
       (.I0(\m_axi_awlen[7] [3]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .I3(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
        .I4(\m_axi_awlen[3]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[4]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[4]_INST_0_i_2 
       (.I0(\m_axi_awlen[7]_0 [4]),
        .I1(din[8]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [4]),
        .I3(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_awlen[4]_INST_0_i_3_n_0 ),
        .O(\m_axi_awlen[4]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_awlen[4]_INST_0_i_3 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_awlen[7]_INST_0_i_6_0 [4]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_awlen[4]_INST_0_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_awlen[5]_INST_0 
       (.I0(\m_axi_awlen[7]_INST_0_i_3_n_0 ),
        .I1(\m_axi_awlen[7] [5]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [5]));
  LUT6 #(
    .INIT(64'hD42BBBBB2BD44444)) 
    \m_axi_awlen[6]_INST_0 
       (.I0(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
        .I1(\m_axi_awlen[7]_INST_0_i_3_n_0 ),
        .I2(\m_axi_awlen[7] [5]),
        .I3(\m_axi_awlen[7] [6]),
        .I4(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I5(\m_axi_awlen[7]_INST_0_i_5_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [6]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \m_axi_awlen[6]_INST_0_i_1 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .O(\m_axi_awlen[6]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7F57150180A8EAFE)) 
    \m_axi_awlen[7]_INST_0 
       (.I0(\m_axi_awlen[7]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7]_INST_0_i_2_n_0 ),
        .I2(\m_axi_awlen[7]_INST_0_i_3_n_0 ),
        .I3(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
        .I4(\m_axi_awlen[7]_INST_0_i_5_n_0 ),
        .I5(\m_axi_awlen[7]_INST_0_i_6_n_0 ),
        .O(\S_AXI_ASIZE_Q_reg[2] [7]));
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_awlen[7]_INST_0_i_1 
       (.I0(\m_axi_awlen[7] [6]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_awlen[7]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8B888B8B8B8B8B8B)) 
    \m_axi_awlen[7]_INST_0_i_10 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_1 [7]),
        .I1(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I2(fix_need_to_split_q),
        .I3(\m_axi_awlen[7]_INST_0_i_6_0 [7]),
        .I4(access_is_wrap_q),
        .I5(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_awlen[7]_INST_0_i_11 
       (.I0(access_is_wrap_q),
        .I1(legal_wrap_len_q),
        .I2(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_awlen[7]_INST_0_i_14 
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_awlen[7]_INST_0_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_awlen[7]_INST_0_i_2 
       (.I0(\m_axi_awlen[7] [5]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_awlen[7]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8000A080E0A0FFE0)) 
    \m_axi_awlen[7]_INST_0_i_3 
       (.I0(\m_axi_awlen[7] [4]),
        .I1(\m_axi_awlen[7] [3]),
        .I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
        .I4(\m_axi_awlen[3]_INST_0_i_2_n_0 ),
        .I5(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[7]_INST_0_i_4 
       (.I0(\m_axi_awlen[7]_0 [5]),
        .I1(din[8]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [5]),
        .I3(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_awlen[7]_INST_0_i_8_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[7]_INST_0_i_5 
       (.I0(\m_axi_awlen[7]_0 [6]),
        .I1(din[8]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [6]),
        .I3(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hDFDFDF202020DF20)) 
    \m_axi_awlen[7]_INST_0_i_6 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .I2(\m_axi_awlen[7] [7]),
        .I3(\m_axi_awlen[7]_INST_0_i_10_n_0 ),
        .I4(din[8]),
        .I5(\m_axi_awlen[7]_0 [7]),
        .O(\m_axi_awlen[7]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAFFAABFAAFFAA)) 
    \m_axi_awlen[7]_INST_0_i_7 
       (.I0(\m_axi_awlen[7]_INST_0_i_11_n_0 ),
        .I1(incr_need_to_split_q),
        .I2(\m_axi_awlen[7]_INST_0_i_5_0 ),
        .I3(access_is_incr_q),
        .I4(\m_axi_awlen[7]_INST_0_i_5_1 ),
        .I5(\m_axi_awlen[7]_INST_0_i_14_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_awlen[7]_INST_0_i_8 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_awlen[7]_INST_0_i_6_0 [5]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_awlen[7]_INST_0_i_9 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_awlen[7]_INST_0_i_6_0 [6]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_awsize[0]_INST_0 
       (.I0(din[8]),
        .I1(din[0]),
        .O(\S_AXI_ASIZE_Q_reg[2] [8]));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_awsize[1]_INST_0 
       (.I0(din[8]),
        .I1(din[1]),
        .O(\S_AXI_ASIZE_Q_reg[2] [9]));
  LUT2 #(
    .INIT(4'hB)) 
    \m_axi_awsize[2]_INST_0 
       (.I0(din[2]),
        .I1(din[8]),
        .O(\S_AXI_ASIZE_Q_reg[2] [10]));
  LUT5 #(
    .INIT(32'h888A8888)) 
    m_axi_awvalid_INST_0
       (.I0(command_ongoing),
        .I1(cmd_push_block),
        .I2(full_0),
        .I3(full),
        .I4(m_axi_awvalid_INST_0_i_1_n_0),
        .O(command_ongoing_reg));
  LUT6 #(
    .INIT(64'hBAABAAAAAAAABAAB)) 
    m_axi_awvalid_INST_0_i_1
       (.I0(cmd_b_empty),
        .I1(m_axi_awvalid_INST_0_i_2_n_0),
        .I2(m_axi_awvalid_INST_0_i_1_0[0]),
        .I3(s_axi_bid[0]),
        .I4(m_axi_awvalid_INST_0_i_1_0[1]),
        .I5(s_axi_bid[1]),
        .O(m_axi_awvalid_INST_0_i_1_n_0));
  LUT4 #(
    .INIT(16'h6FF6)) 
    m_axi_awvalid_INST_0_i_2
       (.I0(m_axi_awvalid_INST_0_i_1_0[3]),
        .I1(s_axi_bid[3]),
        .I2(m_axi_awvalid_INST_0_i_1_0[2]),
        .I3(s_axi_bid[2]),
        .O(m_axi_awvalid_INST_0_i_2_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    m_axi_wvalid_INST_0
       (.I0(s_axi_wvalid),
        .I1(empty),
        .O(m_axi_wvalid));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \queue_id[3]_i_1 
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .O(E));
  LUT6 #(
    .INIT(64'h4444444044444444)) 
    s_axi_wready_INST_0
       (.I0(empty),
        .I1(m_axi_wready),
        .I2(s_axi_wready_0),
        .I3(\USE_WRITE.wr_cmd_mirror ),
        .I4(dout[18]),
        .I5(s_axi_wready_INST_0_i_1_n_0),
        .O(s_axi_wready));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFA80000)) 
    s_axi_wready_INST_0_i_1
       (.I0(\goreg_dm.dout_i_reg[18] [4]),
        .I1(\USE_WRITE.wr_cmd_size [0]),
        .I2(\USE_WRITE.wr_cmd_size [1]),
        .I3(\goreg_dm.dout_i_reg[18] [3]),
        .I4(\USE_WRITE.wr_cmd_size [2]),
        .I5(s_axi_wready_INST_0_i_2_n_0),
        .O(s_axi_wready_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFCF0EEECECE0)) 
    s_axi_wready_INST_0_i_2
       (.I0(\goreg_dm.dout_i_reg[18] [2]),
        .I1(\goreg_dm.dout_i_reg[18] [0]),
        .I2(\USE_WRITE.wr_cmd_size [2]),
        .I3(\USE_WRITE.wr_cmd_size [0]),
        .I4(\USE_WRITE.wr_cmd_size [1]),
        .I5(\goreg_dm.dout_i_reg[18] [1]),
        .O(s_axi_wready_INST_0_i_2_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    split_ongoing_i_1
       (.I0(m_axi_awready),
        .I1(command_ongoing_reg),
        .O(m_axi_awready_0));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_27_a_downsizer" *) 
module axi4_dwtrans_axi_dwidth_converter_v2_1_27_a_downsizer
   (dout,
    empty,
    SR,
    \goreg_dm.dout_i_reg[31] ,
    din,
    S_AXI_AREADY_I_reg_0,
    areset_d,
    command_ongoing_reg_0,
    s_axi_bid,
    m_axi_awlock,
    m_axi_awaddr,
    m_axi_wvalid,
    s_axi_wready,
    E,
    m_axi_awburst,
    D,
    \areset_d_reg[0]_0 ,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    CLK,
    \USE_WRITE.wr_cmd_b_ready ,
    s_axi_awlock,
    s_axi_awsize,
    s_axi_awlen,
    first_mi_word,
    Q,
    s_axi_awvalid,
    m_axi_awready,
    out,
    s_axi_awaddr,
    s_axi_awburst,
    s_axi_wvalid,
    m_axi_wready,
    s_axi_wready_0,
    \current_word_1_reg[4] ,
    \current_word_1_reg[4]_0 ,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1[4]_i_2 ,
    S_AXI_AREADY_I_reg_1,
    S_AXI_AREADY_I_reg_2,
    s_axi_arvalid,
    s_axi_awid,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos);
  output [4:0]dout;
  output empty;
  output [0:0]SR;
  output [18:0]\goreg_dm.dout_i_reg[31] ;
  output [10:0]din;
  output S_AXI_AREADY_I_reg_0;
  output [1:0]areset_d;
  output command_ongoing_reg_0;
  output [3:0]s_axi_bid;
  output [0:0]m_axi_awlock;
  output [63:0]m_axi_awaddr;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]E;
  output [1:0]m_axi_awburst;
  output [4:0]D;
  output \areset_d_reg[0]_0 ;
  output [3:0]m_axi_awcache;
  output [2:0]m_axi_awprot;
  output [3:0]m_axi_awregion;
  output [3:0]m_axi_awqos;
  input CLK;
  input \USE_WRITE.wr_cmd_b_ready ;
  input [0:0]s_axi_awlock;
  input [2:0]s_axi_awsize;
  input [7:0]s_axi_awlen;
  input first_mi_word;
  input [1:0]Q;
  input s_axi_awvalid;
  input m_axi_awready;
  input out;
  input [63:0]s_axi_awaddr;
  input [1:0]s_axi_awburst;
  input s_axi_wvalid;
  input m_axi_wready;
  input s_axi_wready_0;
  input \current_word_1_reg[4] ;
  input \current_word_1_reg[4]_0 ;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1[4]_i_2 ;
  input S_AXI_AREADY_I_reg_1;
  input [0:0]S_AXI_AREADY_I_reg_2;
  input s_axi_arvalid;
  input [3:0]s_axi_awid;
  input [3:0]s_axi_awcache;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awregion;
  input [3:0]s_axi_awqos;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]SR;
  wire \S_AXI_AADDR_Q_reg_n_0_[0] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[10] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[11] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[12] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[13] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[14] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[15] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[16] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[17] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[18] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[19] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[1] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[20] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[21] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[22] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[23] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[24] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[25] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[26] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[27] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[28] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[29] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[2] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[30] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[31] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[32] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[33] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[34] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[35] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[36] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[37] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[38] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[39] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[3] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[40] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[41] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[42] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[43] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[44] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[45] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[46] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[47] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[48] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[49] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[4] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[50] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[51] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[52] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[53] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[54] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[55] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[56] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[57] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[58] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[59] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[5] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[60] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[61] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[62] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[63] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[6] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[7] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[8] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[9] ;
  wire [1:0]S_AXI_ABURST_Q;
  wire [3:0]S_AXI_AID_Q;
  wire \S_AXI_ALEN_Q_reg_n_0_[4] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[5] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[6] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[7] ;
  wire [0:0]S_AXI_ALOCK_Q;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire [0:0]S_AXI_AREADY_I_reg_2;
  wire [2:0]S_AXI_ASIZE_Q;
  wire \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ;
  wire [5:0]\USE_B_CHANNEL.cmd_b_depth_reg ;
  wire \USE_B_CHANNEL.cmd_b_empty_i_i_2_n_0 ;
  wire \USE_B_CHANNEL.cmd_b_queue_n_10 ;
  wire \USE_B_CHANNEL.cmd_b_queue_n_11 ;
  wire \USE_B_CHANNEL.cmd_b_queue_n_9 ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire access_fit_mi_side_q;
  wire access_is_fix;
  wire access_is_fix_q;
  wire access_is_incr;
  wire access_is_incr_q;
  wire access_is_wrap;
  wire access_is_wrap_q;
  wire [1:0]areset_d;
  wire \areset_d_reg[0]_0 ;
  wire cmd_b_empty;
  wire cmd_b_push;
  wire cmd_b_push_block;
  wire [4:2]cmd_mask_i;
  wire cmd_mask_q;
  wire \cmd_mask_q[0]_i_1_n_0 ;
  wire \cmd_mask_q[1]_i_1_n_0 ;
  wire \cmd_mask_q[2]_i_1_n_0 ;
  wire \cmd_mask_q[3]_i_1_n_0 ;
  wire \cmd_mask_q[4]_i_1_n_0 ;
  wire \cmd_mask_q_reg_n_0_[0] ;
  wire \cmd_mask_q_reg_n_0_[1] ;
  wire \cmd_mask_q_reg_n_0_[2] ;
  wire \cmd_mask_q_reg_n_0_[3] ;
  wire \cmd_mask_q_reg_n_0_[4] ;
  wire cmd_push;
  wire cmd_push_block;
  wire cmd_queue_n_31;
  wire cmd_queue_n_32;
  wire cmd_queue_n_33;
  wire cmd_queue_n_34;
  wire cmd_queue_n_35;
  wire cmd_queue_n_36;
  wire cmd_queue_n_38;
  wire cmd_queue_n_39;
  wire cmd_queue_n_40;
  wire cmd_queue_n_41;
  wire cmd_queue_n_44;
  wire cmd_queue_n_45;
  wire cmd_queue_n_54;
  wire cmd_split_i;
  wire command_ongoing;
  wire command_ongoing_reg_0;
  wire \current_word_1[4]_i_2 ;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[4] ;
  wire \current_word_1_reg[4]_0 ;
  wire [10:0]din;
  wire [4:0]dout;
  wire [7:0]downsized_len_q;
  wire \downsized_len_q[0]_i_1_n_0 ;
  wire \downsized_len_q[1]_i_1_n_0 ;
  wire \downsized_len_q[2]_i_1_n_0 ;
  wire \downsized_len_q[3]_i_1_n_0 ;
  wire \downsized_len_q[4]_i_1_n_0 ;
  wire \downsized_len_q[5]_i_1_n_0 ;
  wire \downsized_len_q[6]_i_1_n_0 ;
  wire \downsized_len_q[7]_i_1_n_0 ;
  wire empty;
  wire first_mi_word;
  wire [1:0]fix_len;
  wire [2:0]fix_len_q;
  wire \fix_len_q[2]_i_1__0_n_0 ;
  wire fix_need_to_split;
  wire fix_need_to_split_q;
  wire [18:0]\goreg_dm.dout_i_reg[31] ;
  wire incr_need_to_split;
  wire incr_need_to_split_q;
  wire \inst/full ;
  wire legal_wrap_len_q;
  wire legal_wrap_len_q_i_1_n_0;
  wire legal_wrap_len_q_i_2_n_0;
  wire [63:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire m_axi_wready;
  wire m_axi_wvalid;
  wire [14:0]masked_addr;
  wire [63:0]masked_addr_q;
  wire \masked_addr_q[10]_i_2_n_0 ;
  wire \masked_addr_q[11]_i_2_n_0 ;
  wire \masked_addr_q[3]_i_2_n_0 ;
  wire \masked_addr_q[5]_i_2_n_0 ;
  wire \masked_addr_q[6]_i_2_n_0 ;
  wire \masked_addr_q[7]_i_2_n_0 ;
  wire \masked_addr_q[8]_i_2_n_0 ;
  wire \masked_addr_q[8]_i_3_n_0 ;
  wire \masked_addr_q[9]_i_2_n_0 ;
  wire \masked_addr_q[9]_i_3_n_0 ;
  wire [63:4]next_mi_addr;
  wire next_mi_addr0_carry__0_n_0;
  wire next_mi_addr0_carry__0_n_1;
  wire next_mi_addr0_carry__0_n_10;
  wire next_mi_addr0_carry__0_n_11;
  wire next_mi_addr0_carry__0_n_12;
  wire next_mi_addr0_carry__0_n_13;
  wire next_mi_addr0_carry__0_n_14;
  wire next_mi_addr0_carry__0_n_15;
  wire next_mi_addr0_carry__0_n_2;
  wire next_mi_addr0_carry__0_n_3;
  wire next_mi_addr0_carry__0_n_4;
  wire next_mi_addr0_carry__0_n_5;
  wire next_mi_addr0_carry__0_n_6;
  wire next_mi_addr0_carry__0_n_7;
  wire next_mi_addr0_carry__0_n_8;
  wire next_mi_addr0_carry__0_n_9;
  wire next_mi_addr0_carry__1_n_0;
  wire next_mi_addr0_carry__1_n_1;
  wire next_mi_addr0_carry__1_n_10;
  wire next_mi_addr0_carry__1_n_11;
  wire next_mi_addr0_carry__1_n_12;
  wire next_mi_addr0_carry__1_n_13;
  wire next_mi_addr0_carry__1_n_14;
  wire next_mi_addr0_carry__1_n_15;
  wire next_mi_addr0_carry__1_n_2;
  wire next_mi_addr0_carry__1_n_3;
  wire next_mi_addr0_carry__1_n_4;
  wire next_mi_addr0_carry__1_n_5;
  wire next_mi_addr0_carry__1_n_6;
  wire next_mi_addr0_carry__1_n_7;
  wire next_mi_addr0_carry__1_n_8;
  wire next_mi_addr0_carry__1_n_9;
  wire next_mi_addr0_carry__2_n_0;
  wire next_mi_addr0_carry__2_n_1;
  wire next_mi_addr0_carry__2_n_10;
  wire next_mi_addr0_carry__2_n_11;
  wire next_mi_addr0_carry__2_n_12;
  wire next_mi_addr0_carry__2_n_13;
  wire next_mi_addr0_carry__2_n_14;
  wire next_mi_addr0_carry__2_n_15;
  wire next_mi_addr0_carry__2_n_2;
  wire next_mi_addr0_carry__2_n_3;
  wire next_mi_addr0_carry__2_n_4;
  wire next_mi_addr0_carry__2_n_5;
  wire next_mi_addr0_carry__2_n_6;
  wire next_mi_addr0_carry__2_n_7;
  wire next_mi_addr0_carry__2_n_8;
  wire next_mi_addr0_carry__2_n_9;
  wire next_mi_addr0_carry__3_n_0;
  wire next_mi_addr0_carry__3_n_1;
  wire next_mi_addr0_carry__3_n_10;
  wire next_mi_addr0_carry__3_n_11;
  wire next_mi_addr0_carry__3_n_12;
  wire next_mi_addr0_carry__3_n_13;
  wire next_mi_addr0_carry__3_n_14;
  wire next_mi_addr0_carry__3_n_15;
  wire next_mi_addr0_carry__3_n_2;
  wire next_mi_addr0_carry__3_n_3;
  wire next_mi_addr0_carry__3_n_4;
  wire next_mi_addr0_carry__3_n_5;
  wire next_mi_addr0_carry__3_n_6;
  wire next_mi_addr0_carry__3_n_7;
  wire next_mi_addr0_carry__3_n_8;
  wire next_mi_addr0_carry__3_n_9;
  wire next_mi_addr0_carry__4_n_0;
  wire next_mi_addr0_carry__4_n_1;
  wire next_mi_addr0_carry__4_n_10;
  wire next_mi_addr0_carry__4_n_11;
  wire next_mi_addr0_carry__4_n_12;
  wire next_mi_addr0_carry__4_n_13;
  wire next_mi_addr0_carry__4_n_14;
  wire next_mi_addr0_carry__4_n_15;
  wire next_mi_addr0_carry__4_n_2;
  wire next_mi_addr0_carry__4_n_3;
  wire next_mi_addr0_carry__4_n_4;
  wire next_mi_addr0_carry__4_n_5;
  wire next_mi_addr0_carry__4_n_6;
  wire next_mi_addr0_carry__4_n_7;
  wire next_mi_addr0_carry__4_n_8;
  wire next_mi_addr0_carry__4_n_9;
  wire next_mi_addr0_carry__5_n_11;
  wire next_mi_addr0_carry__5_n_12;
  wire next_mi_addr0_carry__5_n_13;
  wire next_mi_addr0_carry__5_n_14;
  wire next_mi_addr0_carry__5_n_15;
  wire next_mi_addr0_carry__5_n_4;
  wire next_mi_addr0_carry__5_n_5;
  wire next_mi_addr0_carry__5_n_6;
  wire next_mi_addr0_carry__5_n_7;
  wire next_mi_addr0_carry_i_8_n_0;
  wire next_mi_addr0_carry_n_0;
  wire next_mi_addr0_carry_n_1;
  wire next_mi_addr0_carry_n_10;
  wire next_mi_addr0_carry_n_11;
  wire next_mi_addr0_carry_n_12;
  wire next_mi_addr0_carry_n_13;
  wire next_mi_addr0_carry_n_14;
  wire next_mi_addr0_carry_n_15;
  wire next_mi_addr0_carry_n_2;
  wire next_mi_addr0_carry_n_3;
  wire next_mi_addr0_carry_n_4;
  wire next_mi_addr0_carry_n_5;
  wire next_mi_addr0_carry_n_6;
  wire next_mi_addr0_carry_n_7;
  wire next_mi_addr0_carry_n_8;
  wire next_mi_addr0_carry_n_9;
  wire [2:1]num_transactions;
  wire \num_transactions_q[0]_i_1_n_0 ;
  wire \num_transactions_q_reg_n_0_[0] ;
  wire \num_transactions_q_reg_n_0_[1] ;
  wire \num_transactions_q_reg_n_0_[2] ;
  wire out;
  wire [7:0]p_0_in;
  wire [3:0]p_0_in_0;
  wire [10:4]pre_mi_addr;
  wire [63:11]pre_mi_addr__0;
  wire \pushed_commands[7]_i_1_n_0 ;
  wire \pushed_commands[7]_i_3_n_0 ;
  wire [7:0]pushed_commands_reg;
  wire pushed_new_cmd;
  wire s_axi_arvalid;
  wire [63:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [3:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [3:0]s_axi_bid;
  wire s_axi_wready;
  wire s_axi_wready_0;
  wire s_axi_wvalid;
  wire si_full_size;
  wire si_full_size_q;
  wire [6:0]split_addr_mask;
  wire \split_addr_mask_q[2]_i_1_n_0 ;
  wire \split_addr_mask_q_reg_n_0_[0] ;
  wire \split_addr_mask_q_reg_n_0_[12] ;
  wire \split_addr_mask_q_reg_n_0_[1] ;
  wire \split_addr_mask_q_reg_n_0_[2] ;
  wire \split_addr_mask_q_reg_n_0_[3] ;
  wire \split_addr_mask_q_reg_n_0_[4] ;
  wire \split_addr_mask_q_reg_n_0_[5] ;
  wire \split_addr_mask_q_reg_n_0_[6] ;
  wire split_ongoing;
  wire [2:0]unalignment_addr;
  wire [2:0]unalignment_addr_q;
  wire wrap_need_to_split;
  wire wrap_need_to_split_q;
  wire wrap_need_to_split_q_i_2_n_0;
  wire wrap_need_to_split_q_i_3_n_0;
  wire wrap_need_to_split_q_i_4_n_0;
  wire [7:0]wrap_rest_len;
  wire [7:0]wrap_rest_len0;
  wire \wrap_rest_len[1]_i_1_n_0 ;
  wire \wrap_rest_len[7]_i_2_n_0 ;
  wire [7:0]wrap_unaligned_len;
  wire [7:0]wrap_unaligned_len_q;
  wire [7:4]NLW_next_mi_addr0_carry__5_CO_UNCONNECTED;
  wire [7:5]NLW_next_mi_addr0_carry__5_O_UNCONNECTED;

  FDRE \S_AXI_AADDR_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[0]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[10]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[11]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[12]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[13]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[14]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[15]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[16]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[17]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[18]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[19]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[1]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[20]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[21]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[22]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[23]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[24]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[25]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[26]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[27]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[28]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[29]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[2]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[30]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[31]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[32]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[33]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[34]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[35]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[36]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[37]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[38]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[39]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[3]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[40] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[40]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[41] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[41]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[42] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[42]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[43] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[43]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[44] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[44]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[45] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[45]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[46] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[46]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[47] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[47]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[48] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[48]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[49] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[49]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[4]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[50] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[50]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[51] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[51]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[52] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[52]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[53] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[53]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[54] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[54]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[55] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[55]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[56] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[56]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[57] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[57]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[58] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[58]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[59] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[59]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[5]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[60] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[60]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[61] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[61]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[62] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[62]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[63] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[63]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[6]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[7]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[8]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[9]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awburst[0]),
        .Q(S_AXI_ABURST_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awburst[1]),
        .Q(S_AXI_ABURST_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[0]),
        .Q(m_axi_awcache[0]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[1]),
        .Q(m_axi_awcache[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[2]),
        .Q(m_axi_awcache[2]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[3]),
        .Q(m_axi_awcache[3]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[0]),
        .Q(S_AXI_AID_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[1]),
        .Q(S_AXI_AID_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[2]),
        .Q(S_AXI_AID_Q[2]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[3]),
        .Q(S_AXI_AID_Q[3]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[0]),
        .Q(p_0_in_0[0]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[1]),
        .Q(p_0_in_0[1]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[2]),
        .Q(p_0_in_0[2]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[3]),
        .Q(p_0_in_0[3]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[4]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[5]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[6]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[7]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_ALOCK_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlock),
        .Q(S_AXI_ALOCK_Q),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awprot[0]),
        .Q(m_axi_awprot[0]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awprot[1]),
        .Q(m_axi_awprot[1]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awprot[2]),
        .Q(m_axi_awprot[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[0]),
        .Q(m_axi_awqos[0]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[1]),
        .Q(m_axi_awqos[1]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[2]),
        .Q(m_axi_awqos[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[3]),
        .Q(m_axi_awqos[3]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44F4FFF4)) 
    S_AXI_AREADY_I_i_1__0
       (.I0(areset_d[0]),
        .I1(areset_d[1]),
        .I2(S_AXI_AREADY_I_reg_1),
        .I3(S_AXI_AREADY_I_reg_2),
        .I4(s_axi_arvalid),
        .O(\areset_d_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    S_AXI_AREADY_I_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_54),
        .Q(S_AXI_AREADY_I_reg_0),
        .R(SR));
  FDRE \S_AXI_AREGION_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[0]),
        .Q(m_axi_awregion[0]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[1]),
        .Q(m_axi_awregion[1]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[2]),
        .Q(m_axi_awregion[2]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[3]),
        .Q(m_axi_awregion[3]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awsize[0]),
        .Q(S_AXI_ASIZE_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awsize[1]),
        .Q(S_AXI_ASIZE_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awsize[2]),
        .Q(S_AXI_ASIZE_Q[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \USE_B_CHANNEL.cmd_b_depth[0]_i_1 
       (.I0(\USE_B_CHANNEL.cmd_b_depth_reg [0]),
        .O(\USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[0] 
       (.C(CLK),
        .CE(cmd_queue_n_39),
        .D(\USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [0]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[1] 
       (.C(CLK),
        .CE(cmd_queue_n_39),
        .D(cmd_queue_n_35),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [1]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[2] 
       (.C(CLK),
        .CE(cmd_queue_n_39),
        .D(cmd_queue_n_34),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [2]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[3] 
       (.C(CLK),
        .CE(cmd_queue_n_39),
        .D(cmd_queue_n_33),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [3]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[4] 
       (.C(CLK),
        .CE(cmd_queue_n_39),
        .D(cmd_queue_n_32),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [4]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[5] 
       (.C(CLK),
        .CE(cmd_queue_n_39),
        .D(cmd_queue_n_31),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [5]),
        .R(SR));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \USE_B_CHANNEL.cmd_b_empty_i_i_2 
       (.I0(\USE_B_CHANNEL.cmd_b_depth_reg [5]),
        .I1(\USE_B_CHANNEL.cmd_b_depth_reg [4]),
        .I2(\USE_B_CHANNEL.cmd_b_depth_reg [2]),
        .I3(\USE_B_CHANNEL.cmd_b_depth_reg [3]),
        .I4(\USE_B_CHANNEL.cmd_b_depth_reg [1]),
        .I5(\USE_B_CHANNEL.cmd_b_depth_reg [0]),
        .O(\USE_B_CHANNEL.cmd_b_empty_i_i_2_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \USE_B_CHANNEL.cmd_b_empty_i_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_40),
        .Q(cmd_b_empty),
        .S(SR));
  axi4_dwtrans_axi_data_fifo_v2_1_26_axic_fifo \USE_B_CHANNEL.cmd_b_queue 
       (.CLK(CLK),
        .Q(pushed_commands_reg),
        .SR(SR),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_is_fix_q(access_is_fix_q),
        .access_is_fix_q_reg(\USE_B_CHANNEL.cmd_b_queue_n_10 ),
        .access_is_incr_q(access_is_incr_q),
        .access_is_incr_q_reg(\USE_B_CHANNEL.cmd_b_queue_n_9 ),
        .access_is_wrap_q(access_is_wrap_q),
        .din(cmd_split_i),
        .dout(dout),
        .empty(empty),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(\inst/full ),
        .\gpr1.dout_i_reg[1] ({\num_transactions_q_reg_n_0_[2] ,\num_transactions_q_reg_n_0_[1] ,\num_transactions_q_reg_n_0_[0] }),
        .\gpr1.dout_i_reg[1]_0 (p_0_in_0),
        .incr_need_to_split_q(incr_need_to_split_q),
        .out(out),
        .\pushed_commands_reg[7] (\USE_B_CHANNEL.cmd_b_queue_n_11 ),
        .split_ongoing(split_ongoing),
        .wr_en(cmd_b_push),
        .wrap_need_to_split_q(wrap_need_to_split_q));
  FDRE #(
    .INIT(1'b0)) 
    access_fit_mi_side_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[4]),
        .Q(access_fit_mi_side_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT2 #(
    .INIT(4'h1)) 
    access_is_fix_q_i_1
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .O(access_is_fix));
  FDRE #(
    .INIT(1'b0)) 
    access_is_fix_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_fix),
        .Q(access_is_fix_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT2 #(
    .INIT(4'h2)) 
    access_is_incr_q_i_1
       (.I0(s_axi_awburst[0]),
        .I1(s_axi_awburst[1]),
        .O(access_is_incr));
  FDRE #(
    .INIT(1'b0)) 
    access_is_incr_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_incr),
        .Q(access_is_incr_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT2 #(
    .INIT(4'h2)) 
    access_is_wrap_q_i_1
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .O(access_is_wrap));
  FDRE #(
    .INIT(1'b0)) 
    access_is_wrap_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_wrap),
        .Q(access_is_wrap_q),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \areset_d_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(SR),
        .Q(areset_d[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \areset_d_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(areset_d[0]),
        .Q(areset_d[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    cmd_b_push_block_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_38),
        .Q(cmd_b_push_block),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cmd_mask_q[0]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[0]),
        .I4(cmd_mask_q),
        .O(\cmd_mask_q[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEFFFEEE)) 
    \cmd_mask_q[1]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awlen[0]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[1]),
        .I5(cmd_mask_q),
        .O(\cmd_mask_q[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \cmd_mask_q[1]_i_2 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(s_axi_awburst[0]),
        .I2(s_axi_awburst[1]),
        .O(cmd_mask_q));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \cmd_mask_q[2]_i_1 
       (.I0(cmd_mask_i[2]),
        .I1(s_axi_awburst[1]),
        .I2(s_axi_awburst[0]),
        .O(\cmd_mask_q[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \cmd_mask_q[3]_i_1 
       (.I0(\masked_addr_q[3]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awburst[1]),
        .I3(s_axi_awburst[0]),
        .O(\cmd_mask_q[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \cmd_mask_q[4]_i_1 
       (.I0(cmd_mask_i[4]),
        .I1(s_axi_awburst[1]),
        .I2(s_axi_awburst[0]),
        .O(\cmd_mask_q[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT5 #(
    .INIT(32'hFEFFFE00)) 
    \cmd_mask_q[4]_i_2 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awlen[0]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awsize[2]),
        .I4(\masked_addr_q[8]_i_2_n_0 ),
        .O(cmd_mask_i[4]));
  FDRE \cmd_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[0]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[1]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[2]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[3]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[4]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[4] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    cmd_push_block_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_41),
        .Q(cmd_push_block),
        .R(1'b0));
  axi4_dwtrans_axi_data_fifo_v2_1_26_axic_fifo__parameterized0__xdcDup__1 cmd_queue
       (.CLK(CLK),
        .D({cmd_queue_n_31,cmd_queue_n_32,cmd_queue_n_33,cmd_queue_n_34,cmd_queue_n_35}),
        .E(cmd_push),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg ),
        .SR(SR),
        .S_AXI_AREADY_I_reg(S_AXI_AREADY_I_reg_0),
        .S_AXI_AREADY_I_reg_0(areset_d[0]),
        .S_AXI_AREADY_I_reg_1(areset_d[1]),
        .\S_AXI_ASIZE_Q_reg[2] (din),
        .\USE_B_CHANNEL.cmd_b_empty_i_reg (\USE_B_CHANNEL.cmd_b_empty_i_i_2_n_0 ),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(cmd_queue_n_45),
        .\areset_d_reg[0] (cmd_queue_n_54),
        .cmd_b_empty(cmd_b_empty),
        .cmd_b_push_block(cmd_b_push_block),
        .cmd_b_push_block_reg(cmd_queue_n_38),
        .cmd_b_push_block_reg_0(cmd_queue_n_39),
        .cmd_b_push_block_reg_1(cmd_queue_n_40),
        .cmd_push_block(cmd_push_block),
        .cmd_push_block_reg(cmd_queue_n_41),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg_0),
        .command_ongoing_reg_0(\USE_B_CHANNEL.cmd_b_queue_n_9 ),
        .\current_word_1[4]_i_2 (\current_word_1[4]_i_2 ),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[3] (Q),
        .\current_word_1_reg[4] (\current_word_1_reg[4] ),
        .\current_word_1_reg[4]_0 (\current_word_1_reg[4]_0 ),
        .din({cmd_split_i,access_fit_mi_side_q,\cmd_mask_q_reg_n_0_[4] ,\cmd_mask_q_reg_n_0_[3] ,\cmd_mask_q_reg_n_0_[2] ,\cmd_mask_q_reg_n_0_[1] ,\cmd_mask_q_reg_n_0_[0] ,S_AXI_ASIZE_Q}),
        .dout(\goreg_dm.dout_i_reg[31] ),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(\inst/full ),
        .\goreg_dm.dout_i_reg[18] (D),
        .\gpr1.dout_i_reg[15] (\split_addr_mask_q_reg_n_0_[4] ),
        .\gpr1.dout_i_reg[15]_0 ({\S_AXI_AADDR_Q_reg_n_0_[4] ,\S_AXI_AADDR_Q_reg_n_0_[3] ,\S_AXI_AADDR_Q_reg_n_0_[2] ,\S_AXI_AADDR_Q_reg_n_0_[1] ,\S_AXI_AADDR_Q_reg_n_0_[0] }),
        .\gpr1.dout_i_reg[15]_1 (\split_addr_mask_q_reg_n_0_[0] ),
        .\gpr1.dout_i_reg[15]_2 (\split_addr_mask_q_reg_n_0_[1] ),
        .\gpr1.dout_i_reg[15]_3 (\split_addr_mask_q_reg_n_0_[2] ),
        .\gpr1.dout_i_reg[15]_4 (\split_addr_mask_q_reg_n_0_[3] ),
        .\gpr1.dout_i_reg[29] (\split_addr_mask_q_reg_n_0_[12] ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_awlen[2] (unalignment_addr_q),
        .\m_axi_awlen[2]_INST_0_i_3 (fix_len_q),
        .\m_axi_awlen[7] (wrap_unaligned_len_q),
        .\m_axi_awlen[7]_0 ({\S_AXI_ALEN_Q_reg_n_0_[7] ,\S_AXI_ALEN_Q_reg_n_0_[6] ,\S_AXI_ALEN_Q_reg_n_0_[5] ,\S_AXI_ALEN_Q_reg_n_0_[4] ,p_0_in_0}),
        .\m_axi_awlen[7]_INST_0_i_5 (\USE_B_CHANNEL.cmd_b_queue_n_10 ),
        .\m_axi_awlen[7]_INST_0_i_5_0 (\USE_B_CHANNEL.cmd_b_queue_n_11 ),
        .\m_axi_awlen[7]_INST_0_i_6 (wrap_rest_len),
        .\m_axi_awlen[7]_INST_0_i_6_0 (downsized_len_q),
        .m_axi_awready(m_axi_awready),
        .m_axi_awready_0(pushed_new_cmd),
        .m_axi_awvalid_INST_0_i_1(S_AXI_AID_Q),
        .m_axi_wready(m_axi_wready),
        .m_axi_wvalid(m_axi_wvalid),
        .out(out),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_awvalid_0(cmd_queue_n_36),
        .s_axi_bid(s_axi_bid),
        .s_axi_wready(s_axi_wready),
        .s_axi_wready_0(s_axi_wready_0),
        .s_axi_wvalid(s_axi_wvalid),
        .s_axi_wvalid_0(E),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(cmd_queue_n_44),
        .wr_en(cmd_b_push),
        .wrap_need_to_split_q(wrap_need_to_split_q));
  FDRE #(
    .INIT(1'b0)) 
    command_ongoing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_36),
        .Q(command_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'hFAEA)) 
    \downsized_len_q[0]_i_1 
       (.I0(s_axi_awlen[0]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .O(\downsized_len_q[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT5 #(
    .INIT(32'hFFC8F7C0)) 
    \downsized_len_q[1]_i_1 
       (.I0(s_axi_awsize[0]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[1]),
        .I4(s_axi_awlen[0]),
        .O(\downsized_len_q[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT5 #(
    .INIT(32'hB8B8B8F0)) 
    \downsized_len_q[2]_i_1 
       (.I0(\masked_addr_q[6]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awlen[2]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awsize[1]),
        .O(\downsized_len_q[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT5 #(
    .INIT(32'hFAEA0A2A)) 
    \downsized_len_q[3]_i_1 
       (.I0(s_axi_awlen[3]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[1]),
        .I4(\masked_addr_q[7]_i_2_n_0 ),
        .O(\downsized_len_q[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT5 #(
    .INIT(32'hB8B8B8F0)) 
    \downsized_len_q[4]_i_1 
       (.I0(\masked_addr_q[8]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awlen[4]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awsize[1]),
        .O(\downsized_len_q[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT5 #(
    .INIT(32'hFAEA0A2A)) 
    \downsized_len_q[5]_i_1 
       (.I0(s_axi_awlen[5]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[1]),
        .I4(\masked_addr_q[9]_i_2_n_0 ),
        .O(\downsized_len_q[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFAEA0A2A)) 
    \downsized_len_q[6]_i_1 
       (.I0(s_axi_awlen[6]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[1]),
        .I4(\masked_addr_q[10]_i_2_n_0 ),
        .O(\downsized_len_q[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT5 #(
    .INIT(32'hFAEA0A2A)) 
    \downsized_len_q[7]_i_1 
       (.I0(s_axi_awlen[7]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[1]),
        .I4(\masked_addr_q[11]_i_2_n_0 ),
        .O(\downsized_len_q[7]_i_1_n_0 ));
  FDRE \downsized_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[0]_i_1_n_0 ),
        .Q(downsized_len_q[0]),
        .R(SR));
  FDRE \downsized_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[1]_i_1_n_0 ),
        .Q(downsized_len_q[1]),
        .R(SR));
  FDRE \downsized_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[2]_i_1_n_0 ),
        .Q(downsized_len_q[2]),
        .R(SR));
  FDRE \downsized_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[3]_i_1_n_0 ),
        .Q(downsized_len_q[3]),
        .R(SR));
  FDRE \downsized_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[4]_i_1_n_0 ),
        .Q(downsized_len_q[4]),
        .R(SR));
  FDRE \downsized_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[5]_i_1_n_0 ),
        .Q(downsized_len_q[5]),
        .R(SR));
  FDRE \downsized_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[6]_i_1_n_0 ),
        .Q(downsized_len_q[6]),
        .R(SR));
  FDRE \downsized_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[7]_i_1_n_0 ),
        .Q(downsized_len_q[7]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'hC8)) 
    \fix_len_q[0]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[0]),
        .O(fix_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \fix_len_q[1]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .O(fix_len[1]));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \fix_len_q[2]_i_1__0 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[2]),
        .O(\fix_len_q[2]_i_1__0_n_0 ));
  FDRE \fix_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[0]),
        .Q(fix_len_q[0]),
        .R(SR));
  FDRE \fix_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[1]),
        .Q(fix_len_q[1]),
        .R(SR));
  FDRE \fix_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\fix_len_q[2]_i_1__0_n_0 ),
        .Q(fix_len_q[2]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT5 #(
    .INIT(32'h11001000)) 
    fix_need_to_split_q_i_1
       (.I0(s_axi_awburst[0]),
        .I1(s_axi_awburst[1]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[2]),
        .I4(s_axi_awsize[0]),
        .O(fix_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    fix_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_need_to_split),
        .Q(fix_need_to_split_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT5 #(
    .INIT(32'h44444440)) 
    incr_need_to_split_q_i_1
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .I2(\num_transactions_q[0]_i_1_n_0 ),
        .I3(num_transactions[2]),
        .I4(num_transactions[1]),
        .O(incr_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    incr_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(incr_need_to_split),
        .Q(incr_need_to_split_q),
        .R(SR));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAFB)) 
    legal_wrap_len_q_i_1
       (.I0(split_addr_mask[4]),
        .I1(s_axi_awsize[2]),
        .I2(legal_wrap_len_q_i_2_n_0),
        .I3(s_axi_awlen[5]),
        .I4(s_axi_awlen[6]),
        .I5(s_axi_awlen[7]),
        .O(legal_wrap_len_q_i_1_n_0));
  LUT6 #(
    .INIT(64'h00000000001F0F5F)) 
    legal_wrap_len_q_i_2
       (.I0(s_axi_awlen[2]),
        .I1(s_axi_awlen[1]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[3]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[4]),
        .O(legal_wrap_len_q_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    legal_wrap_len_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(legal_wrap_len_q_i_1_n_0),
        .Q(legal_wrap_len_q),
        .R(SR));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_awaddr[0]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[0]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_awaddr[0]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[10]_INST_0 
       (.I0(next_mi_addr[10]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[10]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .O(m_axi_awaddr[10]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[11]_INST_0 
       (.I0(next_mi_addr[11]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[11]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .O(m_axi_awaddr[11]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[12]_INST_0 
       (.I0(next_mi_addr[12]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[12]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .O(m_axi_awaddr[12]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[13]_INST_0 
       (.I0(next_mi_addr[13]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[13]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .O(m_axi_awaddr[13]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[14]_INST_0 
       (.I0(next_mi_addr[14]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[14]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .O(m_axi_awaddr[14]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[15]_INST_0 
       (.I0(next_mi_addr[15]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[15]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .O(m_axi_awaddr[15]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[16]_INST_0 
       (.I0(next_mi_addr[16]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[16]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .O(m_axi_awaddr[16]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[17]_INST_0 
       (.I0(next_mi_addr[17]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[17]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .O(m_axi_awaddr[17]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[18]_INST_0 
       (.I0(next_mi_addr[18]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[18]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .O(m_axi_awaddr[18]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[19]_INST_0 
       (.I0(next_mi_addr[19]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[19]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .O(m_axi_awaddr[19]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_awaddr[1]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[1]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_awaddr[1]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[20]_INST_0 
       (.I0(next_mi_addr[20]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[20]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .O(m_axi_awaddr[20]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[21]_INST_0 
       (.I0(next_mi_addr[21]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[21]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .O(m_axi_awaddr[21]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[22]_INST_0 
       (.I0(next_mi_addr[22]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[22]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .O(m_axi_awaddr[22]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[23]_INST_0 
       (.I0(next_mi_addr[23]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[23]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .O(m_axi_awaddr[23]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[24]_INST_0 
       (.I0(next_mi_addr[24]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[24]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .O(m_axi_awaddr[24]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[25]_INST_0 
       (.I0(next_mi_addr[25]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[25]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .O(m_axi_awaddr[25]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[26]_INST_0 
       (.I0(next_mi_addr[26]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[26]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .O(m_axi_awaddr[26]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[27]_INST_0 
       (.I0(next_mi_addr[27]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[27]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .O(m_axi_awaddr[27]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[28]_INST_0 
       (.I0(next_mi_addr[28]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[28]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .O(m_axi_awaddr[28]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[29]_INST_0 
       (.I0(next_mi_addr[29]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[29]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .O(m_axi_awaddr[29]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_awaddr[2]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[2]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_awaddr[2]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[30]_INST_0 
       (.I0(next_mi_addr[30]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[30]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .O(m_axi_awaddr[30]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[31]_INST_0 
       (.I0(next_mi_addr[31]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[31]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .O(m_axi_awaddr[31]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[32]_INST_0 
       (.I0(next_mi_addr[32]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[32]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .O(m_axi_awaddr[32]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[33]_INST_0 
       (.I0(next_mi_addr[33]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[33]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .O(m_axi_awaddr[33]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[34]_INST_0 
       (.I0(next_mi_addr[34]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[34]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .O(m_axi_awaddr[34]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[35]_INST_0 
       (.I0(next_mi_addr[35]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[35]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .O(m_axi_awaddr[35]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[36]_INST_0 
       (.I0(next_mi_addr[36]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[36]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .O(m_axi_awaddr[36]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[37]_INST_0 
       (.I0(next_mi_addr[37]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[37]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .O(m_axi_awaddr[37]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[38]_INST_0 
       (.I0(next_mi_addr[38]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[38]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .O(m_axi_awaddr[38]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[39]_INST_0 
       (.I0(next_mi_addr[39]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[39]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .O(m_axi_awaddr[39]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_awaddr[3]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[3]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_awaddr[3]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[40]_INST_0 
       (.I0(next_mi_addr[40]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[40]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[40] ),
        .O(m_axi_awaddr[40]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[41]_INST_0 
       (.I0(next_mi_addr[41]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[41]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[41] ),
        .O(m_axi_awaddr[41]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[42]_INST_0 
       (.I0(next_mi_addr[42]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[42]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[42] ),
        .O(m_axi_awaddr[42]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[43]_INST_0 
       (.I0(next_mi_addr[43]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[43]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[43] ),
        .O(m_axi_awaddr[43]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[44]_INST_0 
       (.I0(next_mi_addr[44]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[44]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[44] ),
        .O(m_axi_awaddr[44]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[45]_INST_0 
       (.I0(next_mi_addr[45]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[45]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[45] ),
        .O(m_axi_awaddr[45]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[46]_INST_0 
       (.I0(next_mi_addr[46]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[46]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[46] ),
        .O(m_axi_awaddr[46]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[47]_INST_0 
       (.I0(next_mi_addr[47]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[47]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[47] ),
        .O(m_axi_awaddr[47]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[48]_INST_0 
       (.I0(next_mi_addr[48]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[48]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[48] ),
        .O(m_axi_awaddr[48]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[49]_INST_0 
       (.I0(next_mi_addr[49]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[49]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[49] ),
        .O(m_axi_awaddr[49]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[4]_INST_0 
       (.I0(next_mi_addr[4]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[4]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .O(m_axi_awaddr[4]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[50]_INST_0 
       (.I0(next_mi_addr[50]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[50]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[50] ),
        .O(m_axi_awaddr[50]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[51]_INST_0 
       (.I0(next_mi_addr[51]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[51]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[51] ),
        .O(m_axi_awaddr[51]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[52]_INST_0 
       (.I0(next_mi_addr[52]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[52]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[52] ),
        .O(m_axi_awaddr[52]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[53]_INST_0 
       (.I0(next_mi_addr[53]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[53]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[53] ),
        .O(m_axi_awaddr[53]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[54]_INST_0 
       (.I0(next_mi_addr[54]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[54]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[54] ),
        .O(m_axi_awaddr[54]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[55]_INST_0 
       (.I0(next_mi_addr[55]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[55]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[55] ),
        .O(m_axi_awaddr[55]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[56]_INST_0 
       (.I0(next_mi_addr[56]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[56]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[56] ),
        .O(m_axi_awaddr[56]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[57]_INST_0 
       (.I0(next_mi_addr[57]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[57]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[57] ),
        .O(m_axi_awaddr[57]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[58]_INST_0 
       (.I0(next_mi_addr[58]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[58]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[58] ),
        .O(m_axi_awaddr[58]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[59]_INST_0 
       (.I0(next_mi_addr[59]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[59]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[59] ),
        .O(m_axi_awaddr[59]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[5]_INST_0 
       (.I0(next_mi_addr[5]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[5]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .O(m_axi_awaddr[5]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[60]_INST_0 
       (.I0(next_mi_addr[60]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[60]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[60] ),
        .O(m_axi_awaddr[60]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[61]_INST_0 
       (.I0(next_mi_addr[61]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[61]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[61] ),
        .O(m_axi_awaddr[61]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[62]_INST_0 
       (.I0(next_mi_addr[62]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[62]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[62] ),
        .O(m_axi_awaddr[62]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[63]_INST_0 
       (.I0(next_mi_addr[63]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[63]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[63] ),
        .O(m_axi_awaddr[63]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[6]_INST_0 
       (.I0(next_mi_addr[6]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[6]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .O(m_axi_awaddr[6]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[7]_INST_0 
       (.I0(next_mi_addr[7]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[7]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .O(m_axi_awaddr[7]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[8]_INST_0 
       (.I0(next_mi_addr[8]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[8]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .O(m_axi_awaddr[8]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[9]_INST_0 
       (.I0(next_mi_addr[9]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[9]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .O(m_axi_awaddr[9]));
  LUT5 #(
    .INIT(32'hBABBBABA)) 
    \m_axi_awburst[0]_INST_0 
       (.I0(S_AXI_ABURST_Q[0]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_awburst[0]));
  LUT5 #(
    .INIT(32'h8A888A8A)) 
    \m_axi_awburst[1]_INST_0 
       (.I0(S_AXI_ABURST_Q[1]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_awburst[1]));
  LUT4 #(
    .INIT(16'h0002)) 
    \m_axi_awlock[0]_INST_0 
       (.I0(S_AXI_ALOCK_Q),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(m_axi_awlock));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \masked_addr_q[0]_i_1 
       (.I0(s_axi_awaddr[0]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[0]),
        .O(masked_addr[0]));
  LUT6 #(
    .INIT(64'h00002AAAAAAA2AAA)) 
    \masked_addr_q[10]_i_1 
       (.I0(s_axi_awaddr[10]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[7]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awsize[2]),
        .I5(\masked_addr_q[10]_i_2_n_0 ),
        .O(masked_addr[10]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[10]_i_2 
       (.I0(s_axi_awlen[3]),
        .I1(s_axi_awlen[4]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[5]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[6]),
        .O(\masked_addr_q[10]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    \masked_addr_q[11]_i_1 
       (.I0(s_axi_awaddr[11]),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[11]_i_2_n_0 ),
        .O(masked_addr[11]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[11]_i_2 
       (.I0(s_axi_awlen[4]),
        .I1(s_axi_awlen[5]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[6]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[7]),
        .O(\masked_addr_q[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[12]_i_1 
       (.I0(s_axi_awaddr[12]),
        .I1(\num_transactions_q[0]_i_1_n_0 ),
        .O(masked_addr[12]));
  LUT6 #(
    .INIT(64'h202AAAAAAAAAAAAA)) 
    \masked_addr_q[13]_i_1 
       (.I0(s_axi_awaddr[13]),
        .I1(s_axi_awlen[6]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[7]),
        .I4(s_axi_awsize[1]),
        .I5(s_axi_awsize[2]),
        .O(masked_addr[13]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \masked_addr_q[14]_i_1 
       (.I0(s_axi_awaddr[14]),
        .I1(s_axi_awlen[7]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awsize[1]),
        .I4(s_axi_awsize[2]),
        .O(masked_addr[14]));
  LUT6 #(
    .INIT(64'h0002000000020202)) 
    \masked_addr_q[1]_i_1 
       (.I0(s_axi_awaddr[1]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awlen[0]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[1]),
        .O(masked_addr[1]));
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[2]_i_1 
       (.I0(s_axi_awaddr[2]),
        .I1(cmd_mask_i[2]),
        .O(masked_addr[2]));
  LUT6 #(
    .INIT(64'hFFFFFEAEFAFAFEAE)) 
    \masked_addr_q[2]_i_2 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awlen[2]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[1]),
        .I4(s_axi_awsize[1]),
        .I5(s_axi_awlen[0]),
        .O(cmd_mask_i[2]));
  LUT3 #(
    .INIT(8'h02)) 
    \masked_addr_q[3]_i_1 
       (.I0(s_axi_awaddr[3]),
        .I1(\masked_addr_q[3]_i_2_n_0 ),
        .I2(s_axi_awsize[2]),
        .O(masked_addr[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[3]_i_2 
       (.I0(s_axi_awlen[0]),
        .I1(s_axi_awlen[1]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[2]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[3]),
        .O(\masked_addr_q[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h02020202020202A2)) 
    \masked_addr_q[4]_i_1 
       (.I0(s_axi_awaddr[4]),
        .I1(\masked_addr_q[8]_i_2_n_0 ),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[0]),
        .I5(s_axi_awsize[1]),
        .O(masked_addr[4]));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[5]_i_1 
       (.I0(s_axi_awaddr[5]),
        .I1(\masked_addr_q[5]_i_2_n_0 ),
        .O(masked_addr[5]));
  LUT6 #(
    .INIT(64'hFEAEFFFFFEAE0000)) 
    \masked_addr_q[5]_i_2 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awlen[1]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[0]),
        .I4(s_axi_awsize[2]),
        .I5(\masked_addr_q[9]_i_3_n_0 ),
        .O(\masked_addr_q[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[6]_i_1 
       (.I0(\masked_addr_q[6]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[10]_i_2_n_0 ),
        .I3(s_axi_awaddr[6]),
        .O(masked_addr[6]));
  LUT5 #(
    .INIT(32'hFCBBFC88)) 
    \masked_addr_q[6]_i_2 
       (.I0(s_axi_awlen[0]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[1]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[2]),
        .O(\masked_addr_q[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[7]_i_1 
       (.I0(s_axi_awaddr[7]),
        .I1(\masked_addr_q[7]_i_2_n_0 ),
        .O(masked_addr[7]));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \masked_addr_q[7]_i_2 
       (.I0(\masked_addr_q[3]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[11]_i_2_n_0 ),
        .O(\masked_addr_q[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[8]_i_1 
       (.I0(\masked_addr_q[8]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[8]_i_3_n_0 ),
        .I3(s_axi_awaddr[8]),
        .O(masked_addr[8]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[8]_i_2 
       (.I0(s_axi_awlen[1]),
        .I1(s_axi_awlen[2]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[3]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[4]),
        .O(\masked_addr_q[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAFA0C0C0)) 
    \masked_addr_q[8]_i_3 
       (.I0(s_axi_awlen[5]),
        .I1(s_axi_awlen[6]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[7]),
        .I4(s_axi_awsize[0]),
        .O(\masked_addr_q[8]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[9]_i_1 
       (.I0(s_axi_awaddr[9]),
        .I1(\masked_addr_q[9]_i_2_n_0 ),
        .O(masked_addr[9]));
  LUT6 #(
    .INIT(64'hBBB888B888888888)) 
    \masked_addr_q[9]_i_2 
       (.I0(\masked_addr_q[9]_i_3_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awlen[7]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[6]),
        .I5(s_axi_awsize[1]),
        .O(\masked_addr_q[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[9]_i_3 
       (.I0(s_axi_awlen[2]),
        .I1(s_axi_awlen[3]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[4]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[5]),
        .O(\masked_addr_q[9]_i_3_n_0 ));
  FDRE \masked_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[0]),
        .Q(masked_addr_q[0]),
        .R(SR));
  FDRE \masked_addr_q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[10]),
        .Q(masked_addr_q[10]),
        .R(SR));
  FDRE \masked_addr_q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[11]),
        .Q(masked_addr_q[11]),
        .R(SR));
  FDRE \masked_addr_q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[12]),
        .Q(masked_addr_q[12]),
        .R(SR));
  FDRE \masked_addr_q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[13]),
        .Q(masked_addr_q[13]),
        .R(SR));
  FDRE \masked_addr_q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[14]),
        .Q(masked_addr_q[14]),
        .R(SR));
  FDRE \masked_addr_q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[15]),
        .Q(masked_addr_q[15]),
        .R(SR));
  FDRE \masked_addr_q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[16]),
        .Q(masked_addr_q[16]),
        .R(SR));
  FDRE \masked_addr_q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[17]),
        .Q(masked_addr_q[17]),
        .R(SR));
  FDRE \masked_addr_q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[18]),
        .Q(masked_addr_q[18]),
        .R(SR));
  FDRE \masked_addr_q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[19]),
        .Q(masked_addr_q[19]),
        .R(SR));
  FDRE \masked_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[1]),
        .Q(masked_addr_q[1]),
        .R(SR));
  FDRE \masked_addr_q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[20]),
        .Q(masked_addr_q[20]),
        .R(SR));
  FDRE \masked_addr_q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[21]),
        .Q(masked_addr_q[21]),
        .R(SR));
  FDRE \masked_addr_q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[22]),
        .Q(masked_addr_q[22]),
        .R(SR));
  FDRE \masked_addr_q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[23]),
        .Q(masked_addr_q[23]),
        .R(SR));
  FDRE \masked_addr_q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[24]),
        .Q(masked_addr_q[24]),
        .R(SR));
  FDRE \masked_addr_q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[25]),
        .Q(masked_addr_q[25]),
        .R(SR));
  FDRE \masked_addr_q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[26]),
        .Q(masked_addr_q[26]),
        .R(SR));
  FDRE \masked_addr_q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[27]),
        .Q(masked_addr_q[27]),
        .R(SR));
  FDRE \masked_addr_q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[28]),
        .Q(masked_addr_q[28]),
        .R(SR));
  FDRE \masked_addr_q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[29]),
        .Q(masked_addr_q[29]),
        .R(SR));
  FDRE \masked_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[2]),
        .Q(masked_addr_q[2]),
        .R(SR));
  FDRE \masked_addr_q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[30]),
        .Q(masked_addr_q[30]),
        .R(SR));
  FDRE \masked_addr_q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[31]),
        .Q(masked_addr_q[31]),
        .R(SR));
  FDRE \masked_addr_q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[32]),
        .Q(masked_addr_q[32]),
        .R(SR));
  FDRE \masked_addr_q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[33]),
        .Q(masked_addr_q[33]),
        .R(SR));
  FDRE \masked_addr_q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[34]),
        .Q(masked_addr_q[34]),
        .R(SR));
  FDRE \masked_addr_q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[35]),
        .Q(masked_addr_q[35]),
        .R(SR));
  FDRE \masked_addr_q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[36]),
        .Q(masked_addr_q[36]),
        .R(SR));
  FDRE \masked_addr_q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[37]),
        .Q(masked_addr_q[37]),
        .R(SR));
  FDRE \masked_addr_q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[38]),
        .Q(masked_addr_q[38]),
        .R(SR));
  FDRE \masked_addr_q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[39]),
        .Q(masked_addr_q[39]),
        .R(SR));
  FDRE \masked_addr_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[3]),
        .Q(masked_addr_q[3]),
        .R(SR));
  FDRE \masked_addr_q_reg[40] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[40]),
        .Q(masked_addr_q[40]),
        .R(SR));
  FDRE \masked_addr_q_reg[41] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[41]),
        .Q(masked_addr_q[41]),
        .R(SR));
  FDRE \masked_addr_q_reg[42] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[42]),
        .Q(masked_addr_q[42]),
        .R(SR));
  FDRE \masked_addr_q_reg[43] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[43]),
        .Q(masked_addr_q[43]),
        .R(SR));
  FDRE \masked_addr_q_reg[44] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[44]),
        .Q(masked_addr_q[44]),
        .R(SR));
  FDRE \masked_addr_q_reg[45] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[45]),
        .Q(masked_addr_q[45]),
        .R(SR));
  FDRE \masked_addr_q_reg[46] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[46]),
        .Q(masked_addr_q[46]),
        .R(SR));
  FDRE \masked_addr_q_reg[47] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[47]),
        .Q(masked_addr_q[47]),
        .R(SR));
  FDRE \masked_addr_q_reg[48] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[48]),
        .Q(masked_addr_q[48]),
        .R(SR));
  FDRE \masked_addr_q_reg[49] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[49]),
        .Q(masked_addr_q[49]),
        .R(SR));
  FDRE \masked_addr_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[4]),
        .Q(masked_addr_q[4]),
        .R(SR));
  FDRE \masked_addr_q_reg[50] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[50]),
        .Q(masked_addr_q[50]),
        .R(SR));
  FDRE \masked_addr_q_reg[51] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[51]),
        .Q(masked_addr_q[51]),
        .R(SR));
  FDRE \masked_addr_q_reg[52] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[52]),
        .Q(masked_addr_q[52]),
        .R(SR));
  FDRE \masked_addr_q_reg[53] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[53]),
        .Q(masked_addr_q[53]),
        .R(SR));
  FDRE \masked_addr_q_reg[54] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[54]),
        .Q(masked_addr_q[54]),
        .R(SR));
  FDRE \masked_addr_q_reg[55] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[55]),
        .Q(masked_addr_q[55]),
        .R(SR));
  FDRE \masked_addr_q_reg[56] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[56]),
        .Q(masked_addr_q[56]),
        .R(SR));
  FDRE \masked_addr_q_reg[57] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[57]),
        .Q(masked_addr_q[57]),
        .R(SR));
  FDRE \masked_addr_q_reg[58] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[58]),
        .Q(masked_addr_q[58]),
        .R(SR));
  FDRE \masked_addr_q_reg[59] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[59]),
        .Q(masked_addr_q[59]),
        .R(SR));
  FDRE \masked_addr_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[5]),
        .Q(masked_addr_q[5]),
        .R(SR));
  FDRE \masked_addr_q_reg[60] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[60]),
        .Q(masked_addr_q[60]),
        .R(SR));
  FDRE \masked_addr_q_reg[61] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[61]),
        .Q(masked_addr_q[61]),
        .R(SR));
  FDRE \masked_addr_q_reg[62] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[62]),
        .Q(masked_addr_q[62]),
        .R(SR));
  FDRE \masked_addr_q_reg[63] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[63]),
        .Q(masked_addr_q[63]),
        .R(SR));
  FDRE \masked_addr_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[6]),
        .Q(masked_addr_q[6]),
        .R(SR));
  FDRE \masked_addr_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[7]),
        .Q(masked_addr_q[7]),
        .R(SR));
  FDRE \masked_addr_q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[8]),
        .Q(masked_addr_q[8]),
        .R(SR));
  FDRE \masked_addr_q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[9]),
        .Q(masked_addr_q[9]),
        .R(SR));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry_n_0,next_mi_addr0_carry_n_1,next_mi_addr0_carry_n_2,next_mi_addr0_carry_n_3,next_mi_addr0_carry_n_4,next_mi_addr0_carry_n_5,next_mi_addr0_carry_n_6,next_mi_addr0_carry_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,pre_mi_addr__0[12],1'b0}),
        .O({next_mi_addr0_carry_n_8,next_mi_addr0_carry_n_9,next_mi_addr0_carry_n_10,next_mi_addr0_carry_n_11,next_mi_addr0_carry_n_12,next_mi_addr0_carry_n_13,next_mi_addr0_carry_n_14,next_mi_addr0_carry_n_15}),
        .S({pre_mi_addr__0[18:13],next_mi_addr0_carry_i_8_n_0,pre_mi_addr__0[11]}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__0
       (.CI(next_mi_addr0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__0_n_0,next_mi_addr0_carry__0_n_1,next_mi_addr0_carry__0_n_2,next_mi_addr0_carry__0_n_3,next_mi_addr0_carry__0_n_4,next_mi_addr0_carry__0_n_5,next_mi_addr0_carry__0_n_6,next_mi_addr0_carry__0_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__0_n_8,next_mi_addr0_carry__0_n_9,next_mi_addr0_carry__0_n_10,next_mi_addr0_carry__0_n_11,next_mi_addr0_carry__0_n_12,next_mi_addr0_carry__0_n_13,next_mi_addr0_carry__0_n_14,next_mi_addr0_carry__0_n_15}),
        .S(pre_mi_addr__0[26:19]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[26]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[26]),
        .O(pre_mi_addr__0[26]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[25]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[25]),
        .O(pre_mi_addr__0[25]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[24]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[24]),
        .O(pre_mi_addr__0[24]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[23]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[23]),
        .O(pre_mi_addr__0[23]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[22]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[22]),
        .O(pre_mi_addr__0[22]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[21]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[21]),
        .O(pre_mi_addr__0[21]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[20]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[20]),
        .O(pre_mi_addr__0[20]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_8
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[19]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[19]),
        .O(pre_mi_addr__0[19]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__1
       (.CI(next_mi_addr0_carry__0_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__1_n_0,next_mi_addr0_carry__1_n_1,next_mi_addr0_carry__1_n_2,next_mi_addr0_carry__1_n_3,next_mi_addr0_carry__1_n_4,next_mi_addr0_carry__1_n_5,next_mi_addr0_carry__1_n_6,next_mi_addr0_carry__1_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__1_n_8,next_mi_addr0_carry__1_n_9,next_mi_addr0_carry__1_n_10,next_mi_addr0_carry__1_n_11,next_mi_addr0_carry__1_n_12,next_mi_addr0_carry__1_n_13,next_mi_addr0_carry__1_n_14,next_mi_addr0_carry__1_n_15}),
        .S(pre_mi_addr__0[34:27]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[34]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[34]),
        .O(pre_mi_addr__0[34]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[33]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[33]),
        .O(pre_mi_addr__0[33]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[32]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[32]),
        .O(pre_mi_addr__0[32]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[31]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[31]),
        .O(pre_mi_addr__0[31]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[30]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[30]),
        .O(pre_mi_addr__0[30]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[29]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[29]),
        .O(pre_mi_addr__0[29]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[28]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[28]),
        .O(pre_mi_addr__0[28]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_8
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[27]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[27]),
        .O(pre_mi_addr__0[27]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__2
       (.CI(next_mi_addr0_carry__1_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__2_n_0,next_mi_addr0_carry__2_n_1,next_mi_addr0_carry__2_n_2,next_mi_addr0_carry__2_n_3,next_mi_addr0_carry__2_n_4,next_mi_addr0_carry__2_n_5,next_mi_addr0_carry__2_n_6,next_mi_addr0_carry__2_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__2_n_8,next_mi_addr0_carry__2_n_9,next_mi_addr0_carry__2_n_10,next_mi_addr0_carry__2_n_11,next_mi_addr0_carry__2_n_12,next_mi_addr0_carry__2_n_13,next_mi_addr0_carry__2_n_14,next_mi_addr0_carry__2_n_15}),
        .S(pre_mi_addr__0[42:35]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[42] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[42]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[42]),
        .O(pre_mi_addr__0[42]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[41] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[41]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[41]),
        .O(pre_mi_addr__0[41]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[40] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[40]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[40]),
        .O(pre_mi_addr__0[40]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[39]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[39]),
        .O(pre_mi_addr__0[39]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[38]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[38]),
        .O(pre_mi_addr__0[38]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[37]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[37]),
        .O(pre_mi_addr__0[37]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[36]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[36]),
        .O(pre_mi_addr__0[36]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_8
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[35]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[35]),
        .O(pre_mi_addr__0[35]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__3
       (.CI(next_mi_addr0_carry__2_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__3_n_0,next_mi_addr0_carry__3_n_1,next_mi_addr0_carry__3_n_2,next_mi_addr0_carry__3_n_3,next_mi_addr0_carry__3_n_4,next_mi_addr0_carry__3_n_5,next_mi_addr0_carry__3_n_6,next_mi_addr0_carry__3_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__3_n_8,next_mi_addr0_carry__3_n_9,next_mi_addr0_carry__3_n_10,next_mi_addr0_carry__3_n_11,next_mi_addr0_carry__3_n_12,next_mi_addr0_carry__3_n_13,next_mi_addr0_carry__3_n_14,next_mi_addr0_carry__3_n_15}),
        .S(pre_mi_addr__0[50:43]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[50] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[50]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[50]),
        .O(pre_mi_addr__0[50]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[49] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[49]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[49]),
        .O(pre_mi_addr__0[49]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[48] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[48]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[48]),
        .O(pre_mi_addr__0[48]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[47] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[47]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[47]),
        .O(pre_mi_addr__0[47]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[46] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[46]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[46]),
        .O(pre_mi_addr__0[46]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[45] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[45]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[45]),
        .O(pre_mi_addr__0[45]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[44] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[44]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[44]),
        .O(pre_mi_addr__0[44]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_8
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[43] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[43]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[43]),
        .O(pre_mi_addr__0[43]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__4
       (.CI(next_mi_addr0_carry__3_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__4_n_0,next_mi_addr0_carry__4_n_1,next_mi_addr0_carry__4_n_2,next_mi_addr0_carry__4_n_3,next_mi_addr0_carry__4_n_4,next_mi_addr0_carry__4_n_5,next_mi_addr0_carry__4_n_6,next_mi_addr0_carry__4_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__4_n_8,next_mi_addr0_carry__4_n_9,next_mi_addr0_carry__4_n_10,next_mi_addr0_carry__4_n_11,next_mi_addr0_carry__4_n_12,next_mi_addr0_carry__4_n_13,next_mi_addr0_carry__4_n_14,next_mi_addr0_carry__4_n_15}),
        .S(pre_mi_addr__0[58:51]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[58] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[58]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[58]),
        .O(pre_mi_addr__0[58]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[57] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[57]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[57]),
        .O(pre_mi_addr__0[57]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[56] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[56]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[56]),
        .O(pre_mi_addr__0[56]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[55] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[55]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[55]),
        .O(pre_mi_addr__0[55]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[54] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[54]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[54]),
        .O(pre_mi_addr__0[54]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[53] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[53]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[53]),
        .O(pre_mi_addr__0[53]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[52] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[52]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[52]),
        .O(pre_mi_addr__0[52]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_8
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[51] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[51]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[51]),
        .O(pre_mi_addr__0[51]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__5
       (.CI(next_mi_addr0_carry__4_n_0),
        .CI_TOP(1'b0),
        .CO({NLW_next_mi_addr0_carry__5_CO_UNCONNECTED[7:4],next_mi_addr0_carry__5_n_4,next_mi_addr0_carry__5_n_5,next_mi_addr0_carry__5_n_6,next_mi_addr0_carry__5_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({NLW_next_mi_addr0_carry__5_O_UNCONNECTED[7:5],next_mi_addr0_carry__5_n_11,next_mi_addr0_carry__5_n_12,next_mi_addr0_carry__5_n_13,next_mi_addr0_carry__5_n_14,next_mi_addr0_carry__5_n_15}),
        .S({1'b0,1'b0,1'b0,pre_mi_addr__0[63:59]}));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[63] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[63]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[63]),
        .O(pre_mi_addr__0[63]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[62] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[62]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[62]),
        .O(pre_mi_addr__0[62]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[61] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[61]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[61]),
        .O(pre_mi_addr__0[61]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[60] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[60]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[60]),
        .O(pre_mi_addr__0[60]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[59] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[59]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[59]),
        .O(pre_mi_addr__0[59]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[12]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[12]),
        .O(pre_mi_addr__0[12]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[18]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[18]),
        .O(pre_mi_addr__0[18]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[17]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[17]),
        .O(pre_mi_addr__0[17]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[16]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[16]),
        .O(pre_mi_addr__0[16]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[15]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[15]),
        .O(pre_mi_addr__0[15]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[14]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[14]),
        .O(pre_mi_addr__0[14]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[13]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[13]),
        .O(pre_mi_addr__0[13]));
  LUT6 #(
    .INIT(64'h47444777FFFFFFFF)) 
    next_mi_addr0_carry_i_8
       (.I0(next_mi_addr[12]),
        .I1(cmd_queue_n_44),
        .I2(masked_addr_q[12]),
        .I3(cmd_queue_n_45),
        .I4(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .I5(\split_addr_mask_q_reg_n_0_[12] ),
        .O(next_mi_addr0_carry_i_8_n_0));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_9
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[11]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[11]),
        .O(pre_mi_addr__0[11]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[10]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[10]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[10]),
        .O(pre_mi_addr[10]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[4]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[4] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[4]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[4]),
        .O(pre_mi_addr[4]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[5]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[5] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[5]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[5]),
        .O(pre_mi_addr[5]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[6]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[6] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[6]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[6]),
        .O(pre_mi_addr[6]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[7]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[7]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[7]),
        .O(pre_mi_addr[7]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[8]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[8]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[8]),
        .O(pre_mi_addr[8]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[9]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .I2(cmd_queue_n_45),
        .I3(masked_addr_q[9]),
        .I4(cmd_queue_n_44),
        .I5(next_mi_addr[9]),
        .O(pre_mi_addr[9]));
  FDRE \next_mi_addr_reg[10] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[10]),
        .Q(next_mi_addr[10]),
        .R(SR));
  FDRE \next_mi_addr_reg[11] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_15),
        .Q(next_mi_addr[11]),
        .R(SR));
  FDRE \next_mi_addr_reg[12] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_14),
        .Q(next_mi_addr[12]),
        .R(SR));
  FDRE \next_mi_addr_reg[13] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_13),
        .Q(next_mi_addr[13]),
        .R(SR));
  FDRE \next_mi_addr_reg[14] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_12),
        .Q(next_mi_addr[14]),
        .R(SR));
  FDRE \next_mi_addr_reg[15] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_11),
        .Q(next_mi_addr[15]),
        .R(SR));
  FDRE \next_mi_addr_reg[16] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_10),
        .Q(next_mi_addr[16]),
        .R(SR));
  FDRE \next_mi_addr_reg[17] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_9),
        .Q(next_mi_addr[17]),
        .R(SR));
  FDRE \next_mi_addr_reg[18] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_8),
        .Q(next_mi_addr[18]),
        .R(SR));
  FDRE \next_mi_addr_reg[19] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_15),
        .Q(next_mi_addr[19]),
        .R(SR));
  FDRE \next_mi_addr_reg[20] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_14),
        .Q(next_mi_addr[20]),
        .R(SR));
  FDRE \next_mi_addr_reg[21] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_13),
        .Q(next_mi_addr[21]),
        .R(SR));
  FDRE \next_mi_addr_reg[22] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_12),
        .Q(next_mi_addr[22]),
        .R(SR));
  FDRE \next_mi_addr_reg[23] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_11),
        .Q(next_mi_addr[23]),
        .R(SR));
  FDRE \next_mi_addr_reg[24] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_10),
        .Q(next_mi_addr[24]),
        .R(SR));
  FDRE \next_mi_addr_reg[25] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_9),
        .Q(next_mi_addr[25]),
        .R(SR));
  FDRE \next_mi_addr_reg[26] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_8),
        .Q(next_mi_addr[26]),
        .R(SR));
  FDRE \next_mi_addr_reg[27] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_15),
        .Q(next_mi_addr[27]),
        .R(SR));
  FDRE \next_mi_addr_reg[28] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_14),
        .Q(next_mi_addr[28]),
        .R(SR));
  FDRE \next_mi_addr_reg[29] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_13),
        .Q(next_mi_addr[29]),
        .R(SR));
  FDRE \next_mi_addr_reg[30] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_12),
        .Q(next_mi_addr[30]),
        .R(SR));
  FDRE \next_mi_addr_reg[31] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_11),
        .Q(next_mi_addr[31]),
        .R(SR));
  FDRE \next_mi_addr_reg[32] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_10),
        .Q(next_mi_addr[32]),
        .R(SR));
  FDRE \next_mi_addr_reg[33] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_9),
        .Q(next_mi_addr[33]),
        .R(SR));
  FDRE \next_mi_addr_reg[34] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_8),
        .Q(next_mi_addr[34]),
        .R(SR));
  FDRE \next_mi_addr_reg[35] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_15),
        .Q(next_mi_addr[35]),
        .R(SR));
  FDRE \next_mi_addr_reg[36] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_14),
        .Q(next_mi_addr[36]),
        .R(SR));
  FDRE \next_mi_addr_reg[37] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_13),
        .Q(next_mi_addr[37]),
        .R(SR));
  FDRE \next_mi_addr_reg[38] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_12),
        .Q(next_mi_addr[38]),
        .R(SR));
  FDRE \next_mi_addr_reg[39] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_11),
        .Q(next_mi_addr[39]),
        .R(SR));
  FDRE \next_mi_addr_reg[40] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_10),
        .Q(next_mi_addr[40]),
        .R(SR));
  FDRE \next_mi_addr_reg[41] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_9),
        .Q(next_mi_addr[41]),
        .R(SR));
  FDRE \next_mi_addr_reg[42] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_8),
        .Q(next_mi_addr[42]),
        .R(SR));
  FDRE \next_mi_addr_reg[43] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_15),
        .Q(next_mi_addr[43]),
        .R(SR));
  FDRE \next_mi_addr_reg[44] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_14),
        .Q(next_mi_addr[44]),
        .R(SR));
  FDRE \next_mi_addr_reg[45] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_13),
        .Q(next_mi_addr[45]),
        .R(SR));
  FDRE \next_mi_addr_reg[46] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_12),
        .Q(next_mi_addr[46]),
        .R(SR));
  FDRE \next_mi_addr_reg[47] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_11),
        .Q(next_mi_addr[47]),
        .R(SR));
  FDRE \next_mi_addr_reg[48] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_10),
        .Q(next_mi_addr[48]),
        .R(SR));
  FDRE \next_mi_addr_reg[49] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_9),
        .Q(next_mi_addr[49]),
        .R(SR));
  FDRE \next_mi_addr_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[4]),
        .Q(next_mi_addr[4]),
        .R(SR));
  FDRE \next_mi_addr_reg[50] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_8),
        .Q(next_mi_addr[50]),
        .R(SR));
  FDRE \next_mi_addr_reg[51] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_15),
        .Q(next_mi_addr[51]),
        .R(SR));
  FDRE \next_mi_addr_reg[52] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_14),
        .Q(next_mi_addr[52]),
        .R(SR));
  FDRE \next_mi_addr_reg[53] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_13),
        .Q(next_mi_addr[53]),
        .R(SR));
  FDRE \next_mi_addr_reg[54] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_12),
        .Q(next_mi_addr[54]),
        .R(SR));
  FDRE \next_mi_addr_reg[55] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_11),
        .Q(next_mi_addr[55]),
        .R(SR));
  FDRE \next_mi_addr_reg[56] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_10),
        .Q(next_mi_addr[56]),
        .R(SR));
  FDRE \next_mi_addr_reg[57] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_9),
        .Q(next_mi_addr[57]),
        .R(SR));
  FDRE \next_mi_addr_reg[58] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_8),
        .Q(next_mi_addr[58]),
        .R(SR));
  FDRE \next_mi_addr_reg[59] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_15),
        .Q(next_mi_addr[59]),
        .R(SR));
  FDRE \next_mi_addr_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[5]),
        .Q(next_mi_addr[5]),
        .R(SR));
  FDRE \next_mi_addr_reg[60] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_14),
        .Q(next_mi_addr[60]),
        .R(SR));
  FDRE \next_mi_addr_reg[61] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_13),
        .Q(next_mi_addr[61]),
        .R(SR));
  FDRE \next_mi_addr_reg[62] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_12),
        .Q(next_mi_addr[62]),
        .R(SR));
  FDRE \next_mi_addr_reg[63] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_11),
        .Q(next_mi_addr[63]),
        .R(SR));
  FDRE \next_mi_addr_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[6]),
        .Q(next_mi_addr[6]),
        .R(SR));
  FDRE \next_mi_addr_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[7]),
        .Q(next_mi_addr[7]),
        .R(SR));
  FDRE \next_mi_addr_reg[8] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[8]),
        .Q(next_mi_addr[8]),
        .R(SR));
  FDRE \next_mi_addr_reg[9] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[9]),
        .Q(next_mi_addr[9]),
        .R(SR));
  LUT6 #(
    .INIT(64'hF8A8580800000000)) 
    \num_transactions_q[0]_i_1 
       (.I0(s_axi_awsize[0]),
        .I1(s_axi_awlen[7]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[6]),
        .I4(s_axi_awlen[5]),
        .I5(s_axi_awsize[2]),
        .O(\num_transactions_q[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT5 #(
    .INIT(32'h88800080)) 
    \num_transactions_q[1]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[7]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[6]),
        .O(num_transactions[1]));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \num_transactions_q[2]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[7]),
        .O(num_transactions[2]));
  FDRE \num_transactions_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\num_transactions_q[0]_i_1_n_0 ),
        .Q(\num_transactions_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \num_transactions_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[1]),
        .Q(\num_transactions_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \num_transactions_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[2]),
        .Q(\num_transactions_q_reg_n_0_[2] ),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \pushed_commands[0]_i_1 
       (.I0(pushed_commands_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[1]_i_1 
       (.I0(pushed_commands_reg[0]),
        .I1(pushed_commands_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[2]_i_1 
       (.I0(pushed_commands_reg[2]),
        .I1(pushed_commands_reg[1]),
        .I2(pushed_commands_reg[0]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \pushed_commands[3]_i_1 
       (.I0(pushed_commands_reg[3]),
        .I1(pushed_commands_reg[0]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[2]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \pushed_commands[4]_i_1 
       (.I0(pushed_commands_reg[4]),
        .I1(pushed_commands_reg[2]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[0]),
        .I4(pushed_commands_reg[3]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \pushed_commands[5]_i_1 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[3]),
        .I2(pushed_commands_reg[0]),
        .I3(pushed_commands_reg[1]),
        .I4(pushed_commands_reg[2]),
        .I5(pushed_commands_reg[4]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[6]_i_1 
       (.I0(pushed_commands_reg[6]),
        .I1(\pushed_commands[7]_i_3_n_0 ),
        .O(p_0_in[6]));
  LUT2 #(
    .INIT(4'hB)) 
    \pushed_commands[7]_i_1 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(out),
        .O(\pushed_commands[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[7]_i_2 
       (.I0(pushed_commands_reg[7]),
        .I1(\pushed_commands[7]_i_3_n_0 ),
        .I2(pushed_commands_reg[6]),
        .O(p_0_in[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \pushed_commands[7]_i_3 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[3]),
        .I2(pushed_commands_reg[0]),
        .I3(pushed_commands_reg[1]),
        .I4(pushed_commands_reg[2]),
        .I5(pushed_commands_reg[4]),
        .O(\pushed_commands[7]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[0] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[0]),
        .Q(pushed_commands_reg[0]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[1] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[1]),
        .Q(pushed_commands_reg[1]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[2] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[2]),
        .Q(pushed_commands_reg[2]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[3] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[3]),
        .Q(pushed_commands_reg[3]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[4]),
        .Q(pushed_commands_reg[4]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[5]),
        .Q(pushed_commands_reg[5]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[6]),
        .Q(pushed_commands_reg[6]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[7]),
        .Q(pushed_commands_reg[7]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE \queue_id_reg[0] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[0]),
        .Q(s_axi_bid[0]),
        .R(SR));
  FDRE \queue_id_reg[1] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[1]),
        .Q(s_axi_bid[1]),
        .R(SR));
  FDRE \queue_id_reg[2] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[2]),
        .Q(s_axi_bid[2]),
        .R(SR));
  FDRE \queue_id_reg[3] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[3]),
        .Q(s_axi_bid[3]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'h08)) 
    si_full_size_q_i_1
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[1]),
        .O(si_full_size));
  FDRE #(
    .INIT(1'b0)) 
    si_full_size_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(si_full_size),
        .Q(si_full_size_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \split_addr_mask_q[0]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[0]),
        .O(split_addr_mask[0]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \split_addr_mask_q[1]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .O(split_addr_mask[1]));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \split_addr_mask_q[2]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[0]),
        .O(\split_addr_mask_q[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \split_addr_mask_q[3]_i_1 
       (.I0(s_axi_awsize[2]),
        .O(split_addr_mask[3]));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'h37)) 
    \split_addr_mask_q[4]_i_1 
       (.I0(s_axi_awsize[0]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .O(split_addr_mask[4]));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \split_addr_mask_q[5]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .O(split_addr_mask[5]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \split_addr_mask_q[6]_i_1__0 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[1]),
        .O(split_addr_mask[6]));
  FDRE \split_addr_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[0]),
        .Q(\split_addr_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(1'b1),
        .Q(\split_addr_mask_q_reg_n_0_[12] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[1]),
        .Q(\split_addr_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\split_addr_mask_q[2]_i_1_n_0 ),
        .Q(\split_addr_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[3]),
        .Q(\split_addr_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[4]),
        .Q(\split_addr_mask_q_reg_n_0_[4] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[5]),
        .Q(\split_addr_mask_q_reg_n_0_[5] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[6]),
        .Q(\split_addr_mask_q_reg_n_0_[6] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    split_ongoing_reg
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(cmd_split_i),
        .Q(split_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT4 #(
    .INIT(16'hA080)) 
    \unalignment_addr_q[0]_i_1 
       (.I0(s_axi_awaddr[4]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .O(unalignment_addr[0]));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \unalignment_addr_q[1]_i_1 
       (.I0(s_axi_awaddr[5]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .O(unalignment_addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \unalignment_addr_q[2]_i_1__0 
       (.I0(s_axi_awaddr[6]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awsize[1]),
        .O(unalignment_addr[2]));
  FDRE \unalignment_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[0]),
        .Q(unalignment_addr_q[0]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[1]),
        .Q(unalignment_addr_q[1]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[2]),
        .Q(unalignment_addr_q[2]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT5 #(
    .INIT(32'h000000E0)) 
    wrap_need_to_split_q_i_1
       (.I0(wrap_need_to_split_q_i_2_n_0),
        .I1(wrap_need_to_split_q_i_3_n_0),
        .I2(s_axi_awburst[1]),
        .I3(s_axi_awburst[0]),
        .I4(legal_wrap_len_q_i_1_n_0),
        .O(wrap_need_to_split));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF8F8F8)) 
    wrap_need_to_split_q_i_2
       (.I0(s_axi_awaddr[5]),
        .I1(\masked_addr_q[5]_i_2_n_0 ),
        .I2(wrap_unaligned_len[7]),
        .I3(s_axi_awaddr[7]),
        .I4(\masked_addr_q[7]_i_2_n_0 ),
        .I5(wrap_unaligned_len[4]),
        .O(wrap_need_to_split_q_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    wrap_need_to_split_q_i_3
       (.I0(s_axi_awaddr[9]),
        .I1(\masked_addr_q[9]_i_2_n_0 ),
        .I2(s_axi_awaddr[10]),
        .I3(wrap_need_to_split_q_i_4_n_0),
        .I4(wrap_unaligned_len[0]),
        .I5(wrap_unaligned_len[2]),
        .O(wrap_need_to_split_q_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT5 #(
    .INIT(32'hB8888888)) 
    wrap_need_to_split_q_i_4
       (.I0(\masked_addr_q[10]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[7]),
        .I4(s_axi_awsize[1]),
        .O(wrap_need_to_split_q_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    wrap_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_need_to_split),
        .Q(wrap_need_to_split_q),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \wrap_rest_len[0]_i_1 
       (.I0(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[0]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrap_rest_len[1]_i_1 
       (.I0(wrap_unaligned_len_q[0]),
        .I1(wrap_unaligned_len_q[1]),
        .O(\wrap_rest_len[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wrap_rest_len[2]_i_1 
       (.I0(wrap_unaligned_len_q[2]),
        .I1(wrap_unaligned_len_q[1]),
        .I2(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[2]));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wrap_rest_len[3]_i_1 
       (.I0(wrap_unaligned_len_q[3]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .O(wrap_rest_len0[3]));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \wrap_rest_len[4]_i_1 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[3]),
        .I2(wrap_unaligned_len_q[1]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[2]),
        .O(wrap_rest_len0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \wrap_rest_len[5]_i_1 
       (.I0(wrap_unaligned_len_q[5]),
        .I1(wrap_unaligned_len_q[4]),
        .I2(wrap_unaligned_len_q[2]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[1]),
        .I5(wrap_unaligned_len_q[3]),
        .O(wrap_rest_len0[5]));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wrap_rest_len[6]_i_1 
       (.I0(wrap_unaligned_len_q[6]),
        .I1(\wrap_rest_len[7]_i_2_n_0 ),
        .O(wrap_rest_len0[6]));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wrap_rest_len[7]_i_1 
       (.I0(wrap_unaligned_len_q[7]),
        .I1(wrap_unaligned_len_q[6]),
        .I2(\wrap_rest_len[7]_i_2_n_0 ),
        .O(wrap_rest_len0[7]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wrap_rest_len[7]_i_2 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .I4(wrap_unaligned_len_q[3]),
        .I5(wrap_unaligned_len_q[5]),
        .O(\wrap_rest_len[7]_i_2_n_0 ));
  FDRE \wrap_rest_len_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[0]),
        .Q(wrap_rest_len[0]),
        .R(SR));
  FDRE \wrap_rest_len_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrap_rest_len[1]_i_1_n_0 ),
        .Q(wrap_rest_len[1]),
        .R(SR));
  FDRE \wrap_rest_len_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[2]),
        .Q(wrap_rest_len[2]),
        .R(SR));
  FDRE \wrap_rest_len_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[3]),
        .Q(wrap_rest_len[3]),
        .R(SR));
  FDRE \wrap_rest_len_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[4]),
        .Q(wrap_rest_len[4]),
        .R(SR));
  FDRE \wrap_rest_len_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[5]),
        .Q(wrap_rest_len[5]),
        .R(SR));
  FDRE \wrap_rest_len_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[6]),
        .Q(wrap_rest_len[6]),
        .R(SR));
  FDRE \wrap_rest_len_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[7]),
        .Q(wrap_rest_len[7]),
        .R(SR));
  LUT6 #(
    .INIT(64'hA8A8A8A8A8A8A808)) 
    \wrap_unaligned_len_q[0]_i_1 
       (.I0(s_axi_awaddr[4]),
        .I1(\masked_addr_q[8]_i_2_n_0 ),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[0]),
        .I5(s_axi_awsize[1]),
        .O(wrap_unaligned_len[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[1]_i_1 
       (.I0(s_axi_awaddr[5]),
        .I1(\masked_addr_q[5]_i_2_n_0 ),
        .O(wrap_unaligned_len[1]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[2]_i_1 
       (.I0(\masked_addr_q[6]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[10]_i_2_n_0 ),
        .I3(s_axi_awaddr[6]),
        .O(wrap_unaligned_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[3]_i_1 
       (.I0(s_axi_awaddr[7]),
        .I1(\masked_addr_q[7]_i_2_n_0 ),
        .O(wrap_unaligned_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[4]_i_1 
       (.I0(\masked_addr_q[8]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[8]_i_3_n_0 ),
        .I3(s_axi_awaddr[8]),
        .O(wrap_unaligned_len[4]));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[5]_i_1 
       (.I0(s_axi_awaddr[9]),
        .I1(\masked_addr_q[9]_i_2_n_0 ),
        .O(wrap_unaligned_len[5]));
  LUT6 #(
    .INIT(64'hAAAA800000008000)) 
    \wrap_unaligned_len_q[6]_i_1 
       (.I0(s_axi_awaddr[10]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[7]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awsize[2]),
        .I5(\masked_addr_q[10]_i_2_n_0 ),
        .O(wrap_unaligned_len[6]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \wrap_unaligned_len_q[7]_i_1 
       (.I0(s_axi_awaddr[11]),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[11]_i_2_n_0 ),
        .O(wrap_unaligned_len[7]));
  FDRE \wrap_unaligned_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[0]),
        .Q(wrap_unaligned_len_q[0]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[1]),
        .Q(wrap_unaligned_len_q[1]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[2]),
        .Q(wrap_unaligned_len_q[2]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[3]),
        .Q(wrap_unaligned_len_q[3]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[4]),
        .Q(wrap_unaligned_len_q[4]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[5]),
        .Q(wrap_unaligned_len_q[5]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[6]),
        .Q(wrap_unaligned_len_q[6]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[7]),
        .Q(wrap_unaligned_len_q[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_27_a_downsizer" *) 
module axi4_dwtrans_axi_dwidth_converter_v2_1_27_a_downsizer__parameterized0
   (dout,
    \S_AXI_ASIZE_Q_reg[2]_0 ,
    S_AXI_AREADY_I_reg_0,
    m_axi_arready_0,
    command_ongoing_reg_0,
    E,
    empty_fwft_i_reg,
    empty_fwft_i_reg_0,
    s_axi_rdata,
    s_axi_rid,
    m_axi_arlock,
    m_axi_araddr,
    s_axi_aresetn,
    p_0_in,
    \goreg_dm.dout_i_reg[2] ,
    s_axi_rvalid,
    m_axi_rready,
    m_axi_arburst,
    s_axi_rlast,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    CLK,
    SR,
    s_axi_arlock,
    S_AXI_AREADY_I_reg_1,
    s_axi_arsize,
    s_axi_arlen,
    s_axi_arvalid,
    areset_d,
    m_axi_arready,
    out,
    s_axi_rready,
    m_axi_rvalid,
    p_1_in,
    m_axi_rdata,
    s_axi_araddr,
    \cmd_depth_reg[5]_0 ,
    s_axi_arburst,
    first_mi_word,
    Q,
    s_axi_rvalid_0,
    \current_word_1_reg[3] ,
    s_axi_rdata_0_sp_1,
    \current_word_1_reg[4] ,
    \current_word_1_reg[3]_0 ,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[2] ,
    m_axi_rlast,
    s_axi_arid,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos);
  output [20:0]dout;
  output [10:0]\S_AXI_ASIZE_Q_reg[2]_0 ;
  output S_AXI_AREADY_I_reg_0;
  output m_axi_arready_0;
  output command_ongoing_reg_0;
  output [0:0]E;
  output [0:0]empty_fwft_i_reg;
  output [0:0]empty_fwft_i_reg_0;
  output [255:0]s_axi_rdata;
  output [3:0]s_axi_rid;
  output [0:0]m_axi_arlock;
  output [63:0]m_axi_araddr;
  output [0:0]s_axi_aresetn;
  output [4:0]p_0_in;
  output \goreg_dm.dout_i_reg[2] ;
  output s_axi_rvalid;
  output m_axi_rready;
  output [1:0]m_axi_arburst;
  output s_axi_rlast;
  output [3:0]m_axi_arcache;
  output [2:0]m_axi_arprot;
  output [3:0]m_axi_arregion;
  output [3:0]m_axi_arqos;
  input CLK;
  input [0:0]SR;
  input [0:0]s_axi_arlock;
  input S_AXI_AREADY_I_reg_1;
  input [2:0]s_axi_arsize;
  input [7:0]s_axi_arlen;
  input s_axi_arvalid;
  input [1:0]areset_d;
  input m_axi_arready;
  input out;
  input s_axi_rready;
  input m_axi_rvalid;
  input [255:0]p_1_in;
  input [127:0]m_axi_rdata;
  input [63:0]s_axi_araddr;
  input \cmd_depth_reg[5]_0 ;
  input [1:0]s_axi_arburst;
  input first_mi_word;
  input [0:0]Q;
  input s_axi_rvalid_0;
  input \current_word_1_reg[3] ;
  input s_axi_rdata_0_sp_1;
  input \current_word_1_reg[4] ;
  input \current_word_1_reg[3]_0 ;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1_reg[2] ;
  input m_axi_rlast;
  input [3:0]s_axi_arid;
  input [3:0]s_axi_arcache;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arregion;
  input [3:0]s_axi_arqos;

  wire CLK;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire \S_AXI_AADDR_Q_reg_n_0_[0] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[10] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[11] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[12] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[13] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[14] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[15] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[16] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[17] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[18] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[19] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[1] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[20] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[21] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[22] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[23] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[24] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[25] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[26] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[27] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[28] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[29] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[2] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[30] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[31] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[32] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[33] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[34] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[35] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[36] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[37] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[38] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[39] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[3] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[40] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[41] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[42] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[43] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[44] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[45] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[46] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[47] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[48] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[49] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[4] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[50] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[51] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[52] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[53] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[54] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[55] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[56] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[57] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[58] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[59] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[5] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[60] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[61] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[62] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[63] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[6] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[7] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[8] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[9] ;
  wire [1:0]S_AXI_ABURST_Q;
  wire [3:0]S_AXI_AID_Q;
  wire \S_AXI_ALEN_Q_reg_n_0_[4] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[5] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[6] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[7] ;
  wire [0:0]S_AXI_ALOCK_Q;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire [2:0]S_AXI_ASIZE_Q;
  wire [10:0]\S_AXI_ASIZE_Q_reg[2]_0 ;
  wire access_fit_mi_side_q;
  wire access_is_fix;
  wire access_is_fix_q;
  wire access_is_incr;
  wire access_is_incr_q;
  wire access_is_wrap;
  wire access_is_wrap_q;
  wire [1:0]areset_d;
  wire \cmd_depth[0]_i_1_n_0 ;
  wire [5:0]cmd_depth_reg;
  wire \cmd_depth_reg[5]_0 ;
  wire cmd_empty;
  wire cmd_empty_i_2_n_0;
  wire [4:2]cmd_mask_i;
  wire cmd_mask_q;
  wire \cmd_mask_q[0]_i_1__0_n_0 ;
  wire \cmd_mask_q[1]_i_1__0_n_0 ;
  wire \cmd_mask_q[2]_i_1__0_n_0 ;
  wire \cmd_mask_q[3]_i_1__0_n_0 ;
  wire \cmd_mask_q[4]_i_1__0_n_0 ;
  wire \cmd_mask_q_reg_n_0_[0] ;
  wire \cmd_mask_q_reg_n_0_[1] ;
  wire \cmd_mask_q_reg_n_0_[2] ;
  wire \cmd_mask_q_reg_n_0_[3] ;
  wire \cmd_mask_q_reg_n_0_[4] ;
  wire cmd_push;
  wire cmd_push_block;
  wire cmd_queue_n_303;
  wire cmd_queue_n_304;
  wire cmd_queue_n_305;
  wire cmd_queue_n_316;
  wire cmd_queue_n_34;
  wire cmd_queue_n_35;
  wire cmd_queue_n_36;
  wire cmd_queue_n_37;
  wire cmd_queue_n_38;
  wire cmd_queue_n_39;
  wire cmd_queue_n_42;
  wire cmd_split_i;
  wire command_ongoing;
  wire command_ongoing_reg_0;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire \current_word_1_reg[3] ;
  wire \current_word_1_reg[3]_0 ;
  wire \current_word_1_reg[4] ;
  wire [20:0]dout;
  wire [7:0]downsized_len_q;
  wire \downsized_len_q[0]_i_1__0_n_0 ;
  wire \downsized_len_q[1]_i_1__0_n_0 ;
  wire \downsized_len_q[2]_i_1__0_n_0 ;
  wire \downsized_len_q[3]_i_1__0_n_0 ;
  wire \downsized_len_q[4]_i_1__0_n_0 ;
  wire \downsized_len_q[5]_i_1__0_n_0 ;
  wire \downsized_len_q[6]_i_1__0_n_0 ;
  wire \downsized_len_q[7]_i_1__0_n_0 ;
  wire [0:0]empty_fwft_i_reg;
  wire [0:0]empty_fwft_i_reg_0;
  wire first_mi_word;
  wire [1:0]fix_len;
  wire [2:0]fix_len_q;
  wire \fix_len_q[2]_i_1_n_0 ;
  wire fix_need_to_split;
  wire fix_need_to_split_q;
  wire \goreg_dm.dout_i_reg[2] ;
  wire incr_need_to_split;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire legal_wrap_len_q_i_1__0_n_0;
  wire legal_wrap_len_q_i_2__0_n_0;
  wire [63:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire m_axi_arready_0;
  wire [3:0]m_axi_arregion;
  wire [127:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire m_axi_rvalid;
  wire [14:0]masked_addr;
  wire [63:0]masked_addr_q;
  wire \masked_addr_q[10]_i_2__0_n_0 ;
  wire \masked_addr_q[11]_i_2__0_n_0 ;
  wire \masked_addr_q[5]_i_2__0_n_0 ;
  wire \masked_addr_q[6]_i_2__0_n_0 ;
  wire \masked_addr_q[7]_i_2__0_n_0 ;
  wire \masked_addr_q[8]_i_2__0_n_0 ;
  wire \masked_addr_q[8]_i_3__0_n_0 ;
  wire \masked_addr_q[9]_i_2__0_n_0 ;
  wire \masked_addr_q[9]_i_3__0_n_0 ;
  wire [63:4]next_mi_addr;
  wire next_mi_addr0_carry__0_n_0;
  wire next_mi_addr0_carry__0_n_1;
  wire next_mi_addr0_carry__0_n_10;
  wire next_mi_addr0_carry__0_n_11;
  wire next_mi_addr0_carry__0_n_12;
  wire next_mi_addr0_carry__0_n_13;
  wire next_mi_addr0_carry__0_n_14;
  wire next_mi_addr0_carry__0_n_15;
  wire next_mi_addr0_carry__0_n_2;
  wire next_mi_addr0_carry__0_n_3;
  wire next_mi_addr0_carry__0_n_4;
  wire next_mi_addr0_carry__0_n_5;
  wire next_mi_addr0_carry__0_n_6;
  wire next_mi_addr0_carry__0_n_7;
  wire next_mi_addr0_carry__0_n_8;
  wire next_mi_addr0_carry__0_n_9;
  wire next_mi_addr0_carry__1_n_0;
  wire next_mi_addr0_carry__1_n_1;
  wire next_mi_addr0_carry__1_n_10;
  wire next_mi_addr0_carry__1_n_11;
  wire next_mi_addr0_carry__1_n_12;
  wire next_mi_addr0_carry__1_n_13;
  wire next_mi_addr0_carry__1_n_14;
  wire next_mi_addr0_carry__1_n_15;
  wire next_mi_addr0_carry__1_n_2;
  wire next_mi_addr0_carry__1_n_3;
  wire next_mi_addr0_carry__1_n_4;
  wire next_mi_addr0_carry__1_n_5;
  wire next_mi_addr0_carry__1_n_6;
  wire next_mi_addr0_carry__1_n_7;
  wire next_mi_addr0_carry__1_n_8;
  wire next_mi_addr0_carry__1_n_9;
  wire next_mi_addr0_carry__2_n_0;
  wire next_mi_addr0_carry__2_n_1;
  wire next_mi_addr0_carry__2_n_10;
  wire next_mi_addr0_carry__2_n_11;
  wire next_mi_addr0_carry__2_n_12;
  wire next_mi_addr0_carry__2_n_13;
  wire next_mi_addr0_carry__2_n_14;
  wire next_mi_addr0_carry__2_n_15;
  wire next_mi_addr0_carry__2_n_2;
  wire next_mi_addr0_carry__2_n_3;
  wire next_mi_addr0_carry__2_n_4;
  wire next_mi_addr0_carry__2_n_5;
  wire next_mi_addr0_carry__2_n_6;
  wire next_mi_addr0_carry__2_n_7;
  wire next_mi_addr0_carry__2_n_8;
  wire next_mi_addr0_carry__2_n_9;
  wire next_mi_addr0_carry__3_n_0;
  wire next_mi_addr0_carry__3_n_1;
  wire next_mi_addr0_carry__3_n_10;
  wire next_mi_addr0_carry__3_n_11;
  wire next_mi_addr0_carry__3_n_12;
  wire next_mi_addr0_carry__3_n_13;
  wire next_mi_addr0_carry__3_n_14;
  wire next_mi_addr0_carry__3_n_15;
  wire next_mi_addr0_carry__3_n_2;
  wire next_mi_addr0_carry__3_n_3;
  wire next_mi_addr0_carry__3_n_4;
  wire next_mi_addr0_carry__3_n_5;
  wire next_mi_addr0_carry__3_n_6;
  wire next_mi_addr0_carry__3_n_7;
  wire next_mi_addr0_carry__3_n_8;
  wire next_mi_addr0_carry__3_n_9;
  wire next_mi_addr0_carry__4_n_0;
  wire next_mi_addr0_carry__4_n_1;
  wire next_mi_addr0_carry__4_n_10;
  wire next_mi_addr0_carry__4_n_11;
  wire next_mi_addr0_carry__4_n_12;
  wire next_mi_addr0_carry__4_n_13;
  wire next_mi_addr0_carry__4_n_14;
  wire next_mi_addr0_carry__4_n_15;
  wire next_mi_addr0_carry__4_n_2;
  wire next_mi_addr0_carry__4_n_3;
  wire next_mi_addr0_carry__4_n_4;
  wire next_mi_addr0_carry__4_n_5;
  wire next_mi_addr0_carry__4_n_6;
  wire next_mi_addr0_carry__4_n_7;
  wire next_mi_addr0_carry__4_n_8;
  wire next_mi_addr0_carry__4_n_9;
  wire next_mi_addr0_carry__5_n_11;
  wire next_mi_addr0_carry__5_n_12;
  wire next_mi_addr0_carry__5_n_13;
  wire next_mi_addr0_carry__5_n_14;
  wire next_mi_addr0_carry__5_n_15;
  wire next_mi_addr0_carry__5_n_4;
  wire next_mi_addr0_carry__5_n_5;
  wire next_mi_addr0_carry__5_n_6;
  wire next_mi_addr0_carry__5_n_7;
  wire next_mi_addr0_carry_i_8__0_n_0;
  wire next_mi_addr0_carry_n_0;
  wire next_mi_addr0_carry_n_1;
  wire next_mi_addr0_carry_n_10;
  wire next_mi_addr0_carry_n_11;
  wire next_mi_addr0_carry_n_12;
  wire next_mi_addr0_carry_n_13;
  wire next_mi_addr0_carry_n_14;
  wire next_mi_addr0_carry_n_15;
  wire next_mi_addr0_carry_n_2;
  wire next_mi_addr0_carry_n_3;
  wire next_mi_addr0_carry_n_4;
  wire next_mi_addr0_carry_n_5;
  wire next_mi_addr0_carry_n_6;
  wire next_mi_addr0_carry_n_7;
  wire next_mi_addr0_carry_n_8;
  wire next_mi_addr0_carry_n_9;
  wire [2:1]num_transactions;
  wire [2:0]num_transactions_q;
  wire \num_transactions_q[0]_i_1__0_n_0 ;
  wire out;
  wire [4:0]p_0_in;
  wire [3:0]p_0_in_0;
  wire [7:0]p_0_in__0;
  wire [255:0]p_1_in;
  wire [10:4]pre_mi_addr;
  wire [63:11]pre_mi_addr__0;
  wire \pushed_commands[7]_i_1__0_n_0 ;
  wire \pushed_commands[7]_i_3__0_n_0 ;
  wire [7:0]pushed_commands_reg;
  wire pushed_new_cmd;
  wire [63:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [0:0]s_axi_aresetn;
  wire [3:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [255:0]s_axi_rdata;
  wire s_axi_rdata_0_sn_1;
  wire [3:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire s_axi_rvalid;
  wire s_axi_rvalid_0;
  wire si_full_size;
  wire si_full_size_q;
  wire [6:0]split_addr_mask;
  wire \split_addr_mask_q[2]_i_1__0_n_0 ;
  wire \split_addr_mask_q_reg_n_0_[0] ;
  wire \split_addr_mask_q_reg_n_0_[12] ;
  wire \split_addr_mask_q_reg_n_0_[1] ;
  wire \split_addr_mask_q_reg_n_0_[2] ;
  wire \split_addr_mask_q_reg_n_0_[3] ;
  wire \split_addr_mask_q_reg_n_0_[4] ;
  wire \split_addr_mask_q_reg_n_0_[5] ;
  wire \split_addr_mask_q_reg_n_0_[6] ;
  wire split_ongoing;
  wire [2:0]unalignment_addr;
  wire [2:0]unalignment_addr_q;
  wire wrap_need_to_split;
  wire wrap_need_to_split_q;
  wire wrap_need_to_split_q_i_2__0_n_0;
  wire wrap_need_to_split_q_i_3__0_n_0;
  wire wrap_need_to_split_q_i_4__0_n_0;
  wire [7:0]wrap_rest_len;
  wire [7:0]wrap_rest_len0;
  wire \wrap_rest_len[1]_i_1__0_n_0 ;
  wire \wrap_rest_len[7]_i_2__0_n_0 ;
  wire [7:0]wrap_unaligned_len;
  wire [7:0]wrap_unaligned_len_q;
  wire [7:4]NLW_next_mi_addr0_carry__5_CO_UNCONNECTED;
  wire [7:5]NLW_next_mi_addr0_carry__5_O_UNCONNECTED;

  assign s_axi_rdata_0_sn_1 = s_axi_rdata_0_sp_1;
  FDRE \S_AXI_AADDR_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[0]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[10]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[11]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[12]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[13]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[14]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[15]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[16]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[17]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[18]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[19]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[1]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[20]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[21]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[22]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[23]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[24]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[25]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[26]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[27]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[28]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[29]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[2]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[30]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[31]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[32]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[33]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[34]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[35]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[36]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[37]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[38]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[39]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[3]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[40] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[40]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[41] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[41]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[42] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[42]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[43] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[43]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[44] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[44]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[45] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[45]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[46] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[46]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[47] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[47]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[48] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[48]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[49] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[49]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[4]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[50] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[50]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[51] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[51]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[52] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[52]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[53] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[53]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[54] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[54]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[55] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[55]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[56] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[56]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[57] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[57]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[58] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[58]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[59] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[59]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[5]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[60] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[60]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[61] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[61]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[62] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[62]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[63] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[63]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[6]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[7]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[8]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[9]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arburst[0]),
        .Q(S_AXI_ABURST_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arburst[1]),
        .Q(S_AXI_ABURST_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[0]),
        .Q(m_axi_arcache[0]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[1]),
        .Q(m_axi_arcache[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[2]),
        .Q(m_axi_arcache[2]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[3]),
        .Q(m_axi_arcache[3]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[0]),
        .Q(S_AXI_AID_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[1]),
        .Q(S_AXI_AID_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[2]),
        .Q(S_AXI_AID_Q[2]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[3]),
        .Q(S_AXI_AID_Q[3]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[0]),
        .Q(p_0_in_0[0]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[1]),
        .Q(p_0_in_0[1]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[2]),
        .Q(p_0_in_0[2]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[3]),
        .Q(p_0_in_0[3]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[4]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[5]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[6]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[7]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_ALOCK_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlock),
        .Q(S_AXI_ALOCK_Q),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arprot[0]),
        .Q(m_axi_arprot[0]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arprot[1]),
        .Q(m_axi_arprot[1]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arprot[2]),
        .Q(m_axi_arprot[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[0]),
        .Q(m_axi_arqos[0]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[1]),
        .Q(m_axi_arqos[1]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[2]),
        .Q(m_axi_arqos[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[3]),
        .Q(m_axi_arqos[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    S_AXI_AREADY_I_reg
       (.C(CLK),
        .CE(1'b1),
        .D(S_AXI_AREADY_I_reg_1),
        .Q(S_AXI_AREADY_I_reg_0),
        .R(SR));
  FDRE \S_AXI_AREGION_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[0]),
        .Q(m_axi_arregion[0]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[1]),
        .Q(m_axi_arregion[1]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[2]),
        .Q(m_axi_arregion[2]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[3]),
        .Q(m_axi_arregion[3]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arsize[0]),
        .Q(S_AXI_ASIZE_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arsize[1]),
        .Q(S_AXI_ASIZE_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arsize[2]),
        .Q(S_AXI_ASIZE_Q[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    access_fit_mi_side_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[4]),
        .Q(access_fit_mi_side_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h1)) 
    access_is_fix_q_i_1__0
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arburst[0]),
        .O(access_is_fix));
  FDRE #(
    .INIT(1'b0)) 
    access_is_fix_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_fix),
        .Q(access_is_fix_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT2 #(
    .INIT(4'h2)) 
    access_is_incr_q_i_1__0
       (.I0(s_axi_arburst[0]),
        .I1(s_axi_arburst[1]),
        .O(access_is_incr));
  FDRE #(
    .INIT(1'b0)) 
    access_is_incr_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_incr),
        .Q(access_is_incr_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT2 #(
    .INIT(4'h2)) 
    access_is_wrap_q_i_1__0
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arburst[0]),
        .O(access_is_wrap));
  FDRE #(
    .INIT(1'b0)) 
    access_is_wrap_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_wrap),
        .Q(access_is_wrap_q),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_depth[0]_i_1 
       (.I0(cmd_depth_reg[0]),
        .O(\cmd_depth[0]_i_1_n_0 ));
  FDRE \cmd_depth_reg[0] 
       (.C(CLK),
        .CE(cmd_queue_n_303),
        .D(\cmd_depth[0]_i_1_n_0 ),
        .Q(cmd_depth_reg[0]),
        .R(SR));
  FDRE \cmd_depth_reg[1] 
       (.C(CLK),
        .CE(cmd_queue_n_303),
        .D(cmd_queue_n_38),
        .Q(cmd_depth_reg[1]),
        .R(SR));
  FDRE \cmd_depth_reg[2] 
       (.C(CLK),
        .CE(cmd_queue_n_303),
        .D(cmd_queue_n_37),
        .Q(cmd_depth_reg[2]),
        .R(SR));
  FDRE \cmd_depth_reg[3] 
       (.C(CLK),
        .CE(cmd_queue_n_303),
        .D(cmd_queue_n_36),
        .Q(cmd_depth_reg[3]),
        .R(SR));
  FDRE \cmd_depth_reg[4] 
       (.C(CLK),
        .CE(cmd_queue_n_303),
        .D(cmd_queue_n_35),
        .Q(cmd_depth_reg[4]),
        .R(SR));
  FDRE \cmd_depth_reg[5] 
       (.C(CLK),
        .CE(cmd_queue_n_303),
        .D(cmd_queue_n_34),
        .Q(cmd_depth_reg[5]),
        .R(SR));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    cmd_empty_i_2
       (.I0(cmd_depth_reg[5]),
        .I1(cmd_depth_reg[4]),
        .I2(cmd_depth_reg[2]),
        .I3(cmd_depth_reg[3]),
        .I4(cmd_depth_reg[1]),
        .I5(cmd_depth_reg[0]),
        .O(cmd_empty_i_2_n_0));
  FDSE #(
    .INIT(1'b0)) 
    cmd_empty_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_316),
        .Q(cmd_empty),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cmd_mask_q[0]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[0]),
        .I4(cmd_mask_q),
        .O(\cmd_mask_q[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEFFFEEE)) 
    \cmd_mask_q[1]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arlen[0]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[1]),
        .I5(cmd_mask_q),
        .O(\cmd_mask_q[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \cmd_mask_q[1]_i_2__0 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(s_axi_arburst[0]),
        .I2(s_axi_arburst[1]),
        .O(cmd_mask_q));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \cmd_mask_q[2]_i_1__0 
       (.I0(cmd_mask_i[2]),
        .I1(s_axi_arburst[1]),
        .I2(s_axi_arburst[0]),
        .O(\cmd_mask_q[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \cmd_mask_q[3]_i_1__0 
       (.I0(\masked_addr_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arburst[1]),
        .I3(s_axi_arburst[0]),
        .O(\cmd_mask_q[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \cmd_mask_q[4]_i_1__0 
       (.I0(cmd_mask_i[4]),
        .I1(s_axi_arburst[1]),
        .I2(s_axi_arburst[0]),
        .O(\cmd_mask_q[4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'hFEFFFE00)) 
    \cmd_mask_q[4]_i_2__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arlen[0]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arsize[2]),
        .I4(\masked_addr_q[8]_i_2__0_n_0 ),
        .O(cmd_mask_i[4]));
  FDRE \cmd_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[0]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[1]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[2]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[3]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[4]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[4] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    cmd_push_block_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_42),
        .Q(cmd_push_block),
        .R(1'b0));
  axi4_dwtrans_axi_data_fifo_v2_1_26_axic_fifo__parameterized0 cmd_queue
       (.CLK(CLK),
        .D({cmd_queue_n_34,cmd_queue_n_35,cmd_queue_n_36,cmd_queue_n_37,cmd_queue_n_38}),
        .E(S_AXI_AREADY_I_reg_0),
        .Q(cmd_depth_reg),
        .SR(SR),
        .access_fit_mi_side_q(access_fit_mi_side_q),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(cmd_queue_n_305),
        .areset_d(areset_d),
        .\cmd_depth_reg[5] (\cmd_depth_reg[5]_0 ),
        .cmd_empty(cmd_empty),
        .cmd_empty_reg(cmd_queue_n_316),
        .cmd_empty_reg_0(cmd_empty_i_2_n_0),
        .cmd_push(cmd_push),
        .cmd_push_block(cmd_push_block),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg_0),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[2] (\current_word_1_reg[2] ),
        .\current_word_1_reg[3] (\current_word_1_reg[3] ),
        .\current_word_1_reg[3]_0 (\current_word_1_reg[3]_0 ),
        .\current_word_1_reg[4] (\current_word_1_reg[4] ),
        .din({cmd_split_i,\S_AXI_ASIZE_Q_reg[2]_0 }),
        .dout(dout),
        .empty_fwft_i_reg(E),
        .empty_fwft_i_reg_0(empty_fwft_i_reg),
        .empty_fwft_i_reg_1(empty_fwft_i_reg_0),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .\goreg_dm.dout_i_reg[18] (p_0_in[4]),
        .\goreg_dm.dout_i_reg[2] (\goreg_dm.dout_i_reg[2] ),
        .\gpr1.dout_i_reg[15] ({\cmd_mask_q_reg_n_0_[4] ,\cmd_mask_q_reg_n_0_[3] ,\cmd_mask_q_reg_n_0_[2] ,\cmd_mask_q_reg_n_0_[1] ,\cmd_mask_q_reg_n_0_[0] ,S_AXI_ASIZE_Q}),
        .\gpr1.dout_i_reg[15]_0 (\split_addr_mask_q_reg_n_0_[4] ),
        .\gpr1.dout_i_reg[15]_1 ({\S_AXI_AADDR_Q_reg_n_0_[4] ,\S_AXI_AADDR_Q_reg_n_0_[3] ,\S_AXI_AADDR_Q_reg_n_0_[2] ,\S_AXI_AADDR_Q_reg_n_0_[1] ,\S_AXI_AADDR_Q_reg_n_0_[0] }),
        .\gpr1.dout_i_reg[15]_2 (\split_addr_mask_q_reg_n_0_[0] ),
        .\gpr1.dout_i_reg[15]_3 (\split_addr_mask_q_reg_n_0_[1] ),
        .\gpr1.dout_i_reg[15]_4 (\split_addr_mask_q_reg_n_0_[2] ),
        .\gpr1.dout_i_reg[15]_5 (\split_addr_mask_q_reg_n_0_[3] ),
        .\gpr1.dout_i_reg[29] (\split_addr_mask_q_reg_n_0_[12] ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_arlen[2] (unalignment_addr_q),
        .\m_axi_arlen[2]_INST_0_i_3 (fix_len_q),
        .\m_axi_arlen[7] (wrap_unaligned_len_q),
        .\m_axi_arlen[7]_0 ({\S_AXI_ALEN_Q_reg_n_0_[7] ,\S_AXI_ALEN_Q_reg_n_0_[6] ,\S_AXI_ALEN_Q_reg_n_0_[5] ,\S_AXI_ALEN_Q_reg_n_0_[4] ,p_0_in_0}),
        .\m_axi_arlen[7]_INST_0_i_1 (wrap_rest_len),
        .\m_axi_arlen[7]_INST_0_i_13 (num_transactions_q),
        .\m_axi_arlen[7]_INST_0_i_1_0 (downsized_len_q),
        .\m_axi_arlen[7]_INST_0_i_8 (pushed_commands_reg),
        .m_axi_arready(m_axi_arready),
        .m_axi_arready_0(m_axi_arready_0),
        .m_axi_arready_1(cmd_queue_n_42),
        .m_axi_arready_2(pushed_new_cmd),
        .m_axi_arvalid(S_AXI_AID_Q),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_rvalid_0(cmd_queue_n_303),
        .out(out),
        .p_0_in(p_0_in[3:0]),
        .p_1_in(p_1_in),
        .s_axi_aresetn(s_axi_aresetn),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_arvalid_0(cmd_queue_n_39),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rdata_0_sp_1(s_axi_rdata_0_sn_1),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_rvalid_0(Q),
        .s_axi_rvalid_1(s_axi_rvalid_0),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(cmd_queue_n_304),
        .wrap_need_to_split_q(wrap_need_to_split_q));
  FDRE #(
    .INIT(1'b0)) 
    command_ongoing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_39),
        .Q(command_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'hFAEA)) 
    \downsized_len_q[0]_i_1__0 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .O(\downsized_len_q[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'hFFC8F7C0)) 
    \downsized_len_q[1]_i_1__0 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[1]),
        .I4(s_axi_arlen[0]),
        .O(\downsized_len_q[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'hB8B8B8F0)) 
    \downsized_len_q[2]_i_1__0 
       (.I0(\masked_addr_q[6]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arlen[2]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arsize[1]),
        .O(\downsized_len_q[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT5 #(
    .INIT(32'hB8B8B8F0)) 
    \downsized_len_q[3]_i_1__0 
       (.I0(\masked_addr_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arlen[3]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arsize[1]),
        .O(\downsized_len_q[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT5 #(
    .INIT(32'hB8B8B8F0)) 
    \downsized_len_q[4]_i_1__0 
       (.I0(\masked_addr_q[8]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arlen[4]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arsize[1]),
        .O(\downsized_len_q[4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'hFAEA0A2A)) 
    \downsized_len_q[5]_i_1__0 
       (.I0(s_axi_arlen[5]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[1]),
        .I4(\masked_addr_q[9]_i_2__0_n_0 ),
        .O(\downsized_len_q[5]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFAEA0A2A)) 
    \downsized_len_q[6]_i_1__0 
       (.I0(s_axi_arlen[6]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[1]),
        .I4(\masked_addr_q[10]_i_2__0_n_0 ),
        .O(\downsized_len_q[6]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'hFAEA0A2A)) 
    \downsized_len_q[7]_i_1__0 
       (.I0(s_axi_arlen[7]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[1]),
        .I4(\masked_addr_q[11]_i_2__0_n_0 ),
        .O(\downsized_len_q[7]_i_1__0_n_0 ));
  FDRE \downsized_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[0]_i_1__0_n_0 ),
        .Q(downsized_len_q[0]),
        .R(SR));
  FDRE \downsized_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[1]_i_1__0_n_0 ),
        .Q(downsized_len_q[1]),
        .R(SR));
  FDRE \downsized_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[2]_i_1__0_n_0 ),
        .Q(downsized_len_q[2]),
        .R(SR));
  FDRE \downsized_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[3]_i_1__0_n_0 ),
        .Q(downsized_len_q[3]),
        .R(SR));
  FDRE \downsized_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[4]_i_1__0_n_0 ),
        .Q(downsized_len_q[4]),
        .R(SR));
  FDRE \downsized_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[5]_i_1__0_n_0 ),
        .Q(downsized_len_q[5]),
        .R(SR));
  FDRE \downsized_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[6]_i_1__0_n_0 ),
        .Q(downsized_len_q[6]),
        .R(SR));
  FDRE \downsized_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[7]_i_1__0_n_0 ),
        .Q(downsized_len_q[7]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hC8)) 
    \fix_len_q[0]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[0]),
        .O(fix_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \fix_len_q[1]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .O(fix_len[1]));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \fix_len_q[2]_i_1 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .O(\fix_len_q[2]_i_1_n_0 ));
  FDRE \fix_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[0]),
        .Q(fix_len_q[0]),
        .R(SR));
  FDRE \fix_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[1]),
        .Q(fix_len_q[1]),
        .R(SR));
  FDRE \fix_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\fix_len_q[2]_i_1_n_0 ),
        .Q(fix_len_q[2]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'h11001000)) 
    fix_need_to_split_q_i_1__0
       (.I0(s_axi_arburst[0]),
        .I1(s_axi_arburst[1]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[2]),
        .I4(s_axi_arsize[0]),
        .O(fix_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    fix_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_need_to_split),
        .Q(fix_need_to_split_q),
        .R(SR));
  LUT6 #(
    .INIT(64'hAAAAA88888888888)) 
    incr_need_to_split_q_i_1__0
       (.I0(access_is_incr),
        .I1(\num_transactions_q[0]_i_1__0_n_0 ),
        .I2(s_axi_arlen[6]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[7]),
        .I5(fix_len[1]),
        .O(incr_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    incr_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(incr_need_to_split),
        .Q(incr_need_to_split_q),
        .R(SR));
  LUT6 #(
    .INIT(64'h777F7F7F55775577)) 
    legal_wrap_len_q_i_1__0
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[2]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[1]),
        .I5(legal_wrap_len_q_i_2__0_n_0),
        .O(legal_wrap_len_q_i_1__0_n_0));
  LUT5 #(
    .INIT(32'h00000001)) 
    legal_wrap_len_q_i_2__0
       (.I0(s_axi_arlen[3]),
        .I1(s_axi_arlen[5]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arlen[6]),
        .I4(s_axi_arlen[4]),
        .O(legal_wrap_len_q_i_2__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    legal_wrap_len_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(legal_wrap_len_q_i_1__0_n_0),
        .Q(legal_wrap_len_q),
        .R(SR));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_araddr[0]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[0]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_araddr[0]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[10]_INST_0 
       (.I0(next_mi_addr[10]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[10]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .O(m_axi_araddr[10]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[11]_INST_0 
       (.I0(next_mi_addr[11]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[11]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .O(m_axi_araddr[11]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[12]_INST_0 
       (.I0(next_mi_addr[12]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[12]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .O(m_axi_araddr[12]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[13]_INST_0 
       (.I0(next_mi_addr[13]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[13]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .O(m_axi_araddr[13]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[14]_INST_0 
       (.I0(next_mi_addr[14]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[14]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .O(m_axi_araddr[14]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[15]_INST_0 
       (.I0(next_mi_addr[15]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[15]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .O(m_axi_araddr[15]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[16]_INST_0 
       (.I0(next_mi_addr[16]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[16]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .O(m_axi_araddr[16]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[17]_INST_0 
       (.I0(next_mi_addr[17]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[17]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .O(m_axi_araddr[17]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[18]_INST_0 
       (.I0(next_mi_addr[18]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[18]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .O(m_axi_araddr[18]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[19]_INST_0 
       (.I0(next_mi_addr[19]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[19]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .O(m_axi_araddr[19]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_araddr[1]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[1]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_araddr[1]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[20]_INST_0 
       (.I0(next_mi_addr[20]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[20]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .O(m_axi_araddr[20]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[21]_INST_0 
       (.I0(next_mi_addr[21]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[21]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .O(m_axi_araddr[21]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[22]_INST_0 
       (.I0(next_mi_addr[22]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[22]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .O(m_axi_araddr[22]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[23]_INST_0 
       (.I0(next_mi_addr[23]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[23]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .O(m_axi_araddr[23]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[24]_INST_0 
       (.I0(next_mi_addr[24]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[24]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .O(m_axi_araddr[24]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[25]_INST_0 
       (.I0(next_mi_addr[25]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[25]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .O(m_axi_araddr[25]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[26]_INST_0 
       (.I0(next_mi_addr[26]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[26]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .O(m_axi_araddr[26]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[27]_INST_0 
       (.I0(next_mi_addr[27]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[27]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .O(m_axi_araddr[27]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[28]_INST_0 
       (.I0(next_mi_addr[28]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[28]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .O(m_axi_araddr[28]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[29]_INST_0 
       (.I0(next_mi_addr[29]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[29]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .O(m_axi_araddr[29]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_araddr[2]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[2]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_araddr[2]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[30]_INST_0 
       (.I0(next_mi_addr[30]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[30]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .O(m_axi_araddr[30]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[31]_INST_0 
       (.I0(next_mi_addr[31]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[31]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .O(m_axi_araddr[31]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[32]_INST_0 
       (.I0(next_mi_addr[32]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[32]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .O(m_axi_araddr[32]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[33]_INST_0 
       (.I0(next_mi_addr[33]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[33]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .O(m_axi_araddr[33]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[34]_INST_0 
       (.I0(next_mi_addr[34]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[34]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .O(m_axi_araddr[34]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[35]_INST_0 
       (.I0(next_mi_addr[35]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[35]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .O(m_axi_araddr[35]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[36]_INST_0 
       (.I0(next_mi_addr[36]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[36]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .O(m_axi_araddr[36]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[37]_INST_0 
       (.I0(next_mi_addr[37]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[37]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .O(m_axi_araddr[37]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[38]_INST_0 
       (.I0(next_mi_addr[38]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[38]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .O(m_axi_araddr[38]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[39]_INST_0 
       (.I0(next_mi_addr[39]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[39]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .O(m_axi_araddr[39]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_araddr[3]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[3]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_araddr[3]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[40]_INST_0 
       (.I0(next_mi_addr[40]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[40]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[40] ),
        .O(m_axi_araddr[40]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[41]_INST_0 
       (.I0(next_mi_addr[41]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[41]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[41] ),
        .O(m_axi_araddr[41]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[42]_INST_0 
       (.I0(next_mi_addr[42]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[42]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[42] ),
        .O(m_axi_araddr[42]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[43]_INST_0 
       (.I0(next_mi_addr[43]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[43]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[43] ),
        .O(m_axi_araddr[43]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[44]_INST_0 
       (.I0(next_mi_addr[44]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[44]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[44] ),
        .O(m_axi_araddr[44]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[45]_INST_0 
       (.I0(next_mi_addr[45]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[45]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[45] ),
        .O(m_axi_araddr[45]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[46]_INST_0 
       (.I0(next_mi_addr[46]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[46]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[46] ),
        .O(m_axi_araddr[46]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[47]_INST_0 
       (.I0(next_mi_addr[47]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[47]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[47] ),
        .O(m_axi_araddr[47]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[48]_INST_0 
       (.I0(next_mi_addr[48]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[48]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[48] ),
        .O(m_axi_araddr[48]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[49]_INST_0 
       (.I0(next_mi_addr[49]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[49]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[49] ),
        .O(m_axi_araddr[49]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[4]_INST_0 
       (.I0(next_mi_addr[4]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[4]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .O(m_axi_araddr[4]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[50]_INST_0 
       (.I0(next_mi_addr[50]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[50]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[50] ),
        .O(m_axi_araddr[50]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[51]_INST_0 
       (.I0(next_mi_addr[51]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[51]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[51] ),
        .O(m_axi_araddr[51]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[52]_INST_0 
       (.I0(next_mi_addr[52]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[52]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[52] ),
        .O(m_axi_araddr[52]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[53]_INST_0 
       (.I0(next_mi_addr[53]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[53]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[53] ),
        .O(m_axi_araddr[53]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[54]_INST_0 
       (.I0(next_mi_addr[54]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[54]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[54] ),
        .O(m_axi_araddr[54]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[55]_INST_0 
       (.I0(next_mi_addr[55]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[55]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[55] ),
        .O(m_axi_araddr[55]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[56]_INST_0 
       (.I0(next_mi_addr[56]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[56]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[56] ),
        .O(m_axi_araddr[56]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[57]_INST_0 
       (.I0(next_mi_addr[57]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[57]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[57] ),
        .O(m_axi_araddr[57]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[58]_INST_0 
       (.I0(next_mi_addr[58]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[58]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[58] ),
        .O(m_axi_araddr[58]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[59]_INST_0 
       (.I0(next_mi_addr[59]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[59]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[59] ),
        .O(m_axi_araddr[59]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[5]_INST_0 
       (.I0(next_mi_addr[5]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[5]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .O(m_axi_araddr[5]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[60]_INST_0 
       (.I0(next_mi_addr[60]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[60]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[60] ),
        .O(m_axi_araddr[60]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[61]_INST_0 
       (.I0(next_mi_addr[61]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[61]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[61] ),
        .O(m_axi_araddr[61]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[62]_INST_0 
       (.I0(next_mi_addr[62]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[62]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[62] ),
        .O(m_axi_araddr[62]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[63]_INST_0 
       (.I0(next_mi_addr[63]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[63]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[63] ),
        .O(m_axi_araddr[63]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[6]_INST_0 
       (.I0(next_mi_addr[6]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[6]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .O(m_axi_araddr[6]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[7]_INST_0 
       (.I0(next_mi_addr[7]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[7]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .O(m_axi_araddr[7]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[8]_INST_0 
       (.I0(next_mi_addr[8]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[8]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .O(m_axi_araddr[8]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[9]_INST_0 
       (.I0(next_mi_addr[9]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[9]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .O(m_axi_araddr[9]));
  LUT5 #(
    .INIT(32'hBABBBABA)) 
    \m_axi_arburst[0]_INST_0 
       (.I0(S_AXI_ABURST_Q[0]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_arburst[0]));
  LUT5 #(
    .INIT(32'h8A888A8A)) 
    \m_axi_arburst[1]_INST_0 
       (.I0(S_AXI_ABURST_Q[1]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_arburst[1]));
  LUT4 #(
    .INIT(16'h0002)) 
    \m_axi_arlock[0]_INST_0 
       (.I0(S_AXI_ALOCK_Q),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(m_axi_arlock));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \masked_addr_q[0]_i_1__0 
       (.I0(s_axi_araddr[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[0]),
        .O(masked_addr[0]));
  LUT6 #(
    .INIT(64'h00002AAAAAAA2AAA)) 
    \masked_addr_q[10]_i_1__0 
       (.I0(s_axi_araddr[10]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arsize[2]),
        .I5(\masked_addr_q[10]_i_2__0_n_0 ),
        .O(masked_addr[10]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[10]_i_2__0 
       (.I0(s_axi_arlen[3]),
        .I1(s_axi_arlen[4]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[5]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[6]),
        .O(\masked_addr_q[10]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    \masked_addr_q[11]_i_1__0 
       (.I0(s_axi_araddr[11]),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[11]_i_2__0_n_0 ),
        .O(masked_addr[11]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[11]_i_2__0 
       (.I0(s_axi_arlen[4]),
        .I1(s_axi_arlen[5]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[6]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[7]),
        .O(\masked_addr_q[11]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[12]_i_1__0 
       (.I0(s_axi_araddr[12]),
        .I1(\num_transactions_q[0]_i_1__0_n_0 ),
        .O(masked_addr[12]));
  LUT6 #(
    .INIT(64'h202AAAAAAAAAAAAA)) 
    \masked_addr_q[13]_i_1__0 
       (.I0(s_axi_araddr[13]),
        .I1(s_axi_arlen[6]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[7]),
        .I4(s_axi_arsize[1]),
        .I5(s_axi_arsize[2]),
        .O(masked_addr[13]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \masked_addr_q[14]_i_1__0 
       (.I0(s_axi_araddr[14]),
        .I1(s_axi_arlen[7]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arsize[1]),
        .I4(s_axi_arsize[2]),
        .O(masked_addr[14]));
  LUT6 #(
    .INIT(64'h0002000000020202)) 
    \masked_addr_q[1]_i_1__0 
       (.I0(s_axi_araddr[1]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arlen[0]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[1]),
        .O(masked_addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[2]_i_1__0 
       (.I0(s_axi_araddr[2]),
        .I1(cmd_mask_i[2]),
        .O(masked_addr[2]));
  LUT6 #(
    .INIT(64'hFFFFFEAEFAFAFEAE)) 
    \masked_addr_q[2]_i_2__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arlen[2]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[1]),
        .I4(s_axi_arsize[1]),
        .I5(s_axi_arlen[0]),
        .O(cmd_mask_i[2]));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \masked_addr_q[3]_i_1__0 
       (.I0(s_axi_araddr[3]),
        .I1(\masked_addr_q[7]_i_2__0_n_0 ),
        .I2(s_axi_arsize[2]),
        .O(masked_addr[3]));
  LUT6 #(
    .INIT(64'h02020202020202A2)) 
    \masked_addr_q[4]_i_1__0 
       (.I0(s_axi_araddr[4]),
        .I1(\masked_addr_q[8]_i_2__0_n_0 ),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[0]),
        .I5(s_axi_arsize[1]),
        .O(masked_addr[4]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[5]_i_1__0 
       (.I0(s_axi_araddr[5]),
        .I1(\masked_addr_q[5]_i_2__0_n_0 ),
        .O(masked_addr[5]));
  LUT6 #(
    .INIT(64'hFEAEFFFFFEAE0000)) 
    \masked_addr_q[5]_i_2__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arlen[1]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[0]),
        .I4(s_axi_arsize[2]),
        .I5(\masked_addr_q[9]_i_3__0_n_0 ),
        .O(\masked_addr_q[5]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[6]_i_1__0 
       (.I0(\masked_addr_q[6]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[10]_i_2__0_n_0 ),
        .I3(s_axi_araddr[6]),
        .O(masked_addr[6]));
  LUT5 #(
    .INIT(32'hFCBBFC88)) 
    \masked_addr_q[6]_i_2__0 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[1]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[2]),
        .O(\masked_addr_q[6]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[7]_i_1__0 
       (.I0(\masked_addr_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[11]_i_2__0_n_0 ),
        .I3(s_axi_araddr[7]),
        .O(masked_addr[7]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[7]_i_2__0 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arlen[1]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[2]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[3]),
        .O(\masked_addr_q[7]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[8]_i_1__0 
       (.I0(\masked_addr_q[8]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[8]_i_3__0_n_0 ),
        .I3(s_axi_araddr[8]),
        .O(masked_addr[8]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[8]_i_2__0 
       (.I0(s_axi_arlen[1]),
        .I1(s_axi_arlen[2]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[3]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[4]),
        .O(\masked_addr_q[8]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hAFA0C0C0)) 
    \masked_addr_q[8]_i_3__0 
       (.I0(s_axi_arlen[5]),
        .I1(s_axi_arlen[6]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[7]),
        .I4(s_axi_arsize[0]),
        .O(\masked_addr_q[8]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[9]_i_1__0 
       (.I0(s_axi_araddr[9]),
        .I1(\masked_addr_q[9]_i_2__0_n_0 ),
        .O(masked_addr[9]));
  LUT6 #(
    .INIT(64'hBBB888B888888888)) 
    \masked_addr_q[9]_i_2__0 
       (.I0(\masked_addr_q[9]_i_3__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[6]),
        .I5(s_axi_arsize[1]),
        .O(\masked_addr_q[9]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[9]_i_3__0 
       (.I0(s_axi_arlen[2]),
        .I1(s_axi_arlen[3]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[4]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[5]),
        .O(\masked_addr_q[9]_i_3__0_n_0 ));
  FDRE \masked_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[0]),
        .Q(masked_addr_q[0]),
        .R(SR));
  FDRE \masked_addr_q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[10]),
        .Q(masked_addr_q[10]),
        .R(SR));
  FDRE \masked_addr_q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[11]),
        .Q(masked_addr_q[11]),
        .R(SR));
  FDRE \masked_addr_q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[12]),
        .Q(masked_addr_q[12]),
        .R(SR));
  FDRE \masked_addr_q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[13]),
        .Q(masked_addr_q[13]),
        .R(SR));
  FDRE \masked_addr_q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[14]),
        .Q(masked_addr_q[14]),
        .R(SR));
  FDRE \masked_addr_q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[15]),
        .Q(masked_addr_q[15]),
        .R(SR));
  FDRE \masked_addr_q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[16]),
        .Q(masked_addr_q[16]),
        .R(SR));
  FDRE \masked_addr_q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[17]),
        .Q(masked_addr_q[17]),
        .R(SR));
  FDRE \masked_addr_q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[18]),
        .Q(masked_addr_q[18]),
        .R(SR));
  FDRE \masked_addr_q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[19]),
        .Q(masked_addr_q[19]),
        .R(SR));
  FDRE \masked_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[1]),
        .Q(masked_addr_q[1]),
        .R(SR));
  FDRE \masked_addr_q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[20]),
        .Q(masked_addr_q[20]),
        .R(SR));
  FDRE \masked_addr_q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[21]),
        .Q(masked_addr_q[21]),
        .R(SR));
  FDRE \masked_addr_q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[22]),
        .Q(masked_addr_q[22]),
        .R(SR));
  FDRE \masked_addr_q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[23]),
        .Q(masked_addr_q[23]),
        .R(SR));
  FDRE \masked_addr_q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[24]),
        .Q(masked_addr_q[24]),
        .R(SR));
  FDRE \masked_addr_q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[25]),
        .Q(masked_addr_q[25]),
        .R(SR));
  FDRE \masked_addr_q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[26]),
        .Q(masked_addr_q[26]),
        .R(SR));
  FDRE \masked_addr_q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[27]),
        .Q(masked_addr_q[27]),
        .R(SR));
  FDRE \masked_addr_q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[28]),
        .Q(masked_addr_q[28]),
        .R(SR));
  FDRE \masked_addr_q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[29]),
        .Q(masked_addr_q[29]),
        .R(SR));
  FDRE \masked_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[2]),
        .Q(masked_addr_q[2]),
        .R(SR));
  FDRE \masked_addr_q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[30]),
        .Q(masked_addr_q[30]),
        .R(SR));
  FDRE \masked_addr_q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[31]),
        .Q(masked_addr_q[31]),
        .R(SR));
  FDRE \masked_addr_q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[32]),
        .Q(masked_addr_q[32]),
        .R(SR));
  FDRE \masked_addr_q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[33]),
        .Q(masked_addr_q[33]),
        .R(SR));
  FDRE \masked_addr_q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[34]),
        .Q(masked_addr_q[34]),
        .R(SR));
  FDRE \masked_addr_q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[35]),
        .Q(masked_addr_q[35]),
        .R(SR));
  FDRE \masked_addr_q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[36]),
        .Q(masked_addr_q[36]),
        .R(SR));
  FDRE \masked_addr_q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[37]),
        .Q(masked_addr_q[37]),
        .R(SR));
  FDRE \masked_addr_q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[38]),
        .Q(masked_addr_q[38]),
        .R(SR));
  FDRE \masked_addr_q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[39]),
        .Q(masked_addr_q[39]),
        .R(SR));
  FDRE \masked_addr_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[3]),
        .Q(masked_addr_q[3]),
        .R(SR));
  FDRE \masked_addr_q_reg[40] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[40]),
        .Q(masked_addr_q[40]),
        .R(SR));
  FDRE \masked_addr_q_reg[41] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[41]),
        .Q(masked_addr_q[41]),
        .R(SR));
  FDRE \masked_addr_q_reg[42] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[42]),
        .Q(masked_addr_q[42]),
        .R(SR));
  FDRE \masked_addr_q_reg[43] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[43]),
        .Q(masked_addr_q[43]),
        .R(SR));
  FDRE \masked_addr_q_reg[44] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[44]),
        .Q(masked_addr_q[44]),
        .R(SR));
  FDRE \masked_addr_q_reg[45] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[45]),
        .Q(masked_addr_q[45]),
        .R(SR));
  FDRE \masked_addr_q_reg[46] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[46]),
        .Q(masked_addr_q[46]),
        .R(SR));
  FDRE \masked_addr_q_reg[47] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[47]),
        .Q(masked_addr_q[47]),
        .R(SR));
  FDRE \masked_addr_q_reg[48] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[48]),
        .Q(masked_addr_q[48]),
        .R(SR));
  FDRE \masked_addr_q_reg[49] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[49]),
        .Q(masked_addr_q[49]),
        .R(SR));
  FDRE \masked_addr_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[4]),
        .Q(masked_addr_q[4]),
        .R(SR));
  FDRE \masked_addr_q_reg[50] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[50]),
        .Q(masked_addr_q[50]),
        .R(SR));
  FDRE \masked_addr_q_reg[51] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[51]),
        .Q(masked_addr_q[51]),
        .R(SR));
  FDRE \masked_addr_q_reg[52] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[52]),
        .Q(masked_addr_q[52]),
        .R(SR));
  FDRE \masked_addr_q_reg[53] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[53]),
        .Q(masked_addr_q[53]),
        .R(SR));
  FDRE \masked_addr_q_reg[54] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[54]),
        .Q(masked_addr_q[54]),
        .R(SR));
  FDRE \masked_addr_q_reg[55] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[55]),
        .Q(masked_addr_q[55]),
        .R(SR));
  FDRE \masked_addr_q_reg[56] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[56]),
        .Q(masked_addr_q[56]),
        .R(SR));
  FDRE \masked_addr_q_reg[57] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[57]),
        .Q(masked_addr_q[57]),
        .R(SR));
  FDRE \masked_addr_q_reg[58] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[58]),
        .Q(masked_addr_q[58]),
        .R(SR));
  FDRE \masked_addr_q_reg[59] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[59]),
        .Q(masked_addr_q[59]),
        .R(SR));
  FDRE \masked_addr_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[5]),
        .Q(masked_addr_q[5]),
        .R(SR));
  FDRE \masked_addr_q_reg[60] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[60]),
        .Q(masked_addr_q[60]),
        .R(SR));
  FDRE \masked_addr_q_reg[61] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[61]),
        .Q(masked_addr_q[61]),
        .R(SR));
  FDRE \masked_addr_q_reg[62] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[62]),
        .Q(masked_addr_q[62]),
        .R(SR));
  FDRE \masked_addr_q_reg[63] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[63]),
        .Q(masked_addr_q[63]),
        .R(SR));
  FDRE \masked_addr_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[6]),
        .Q(masked_addr_q[6]),
        .R(SR));
  FDRE \masked_addr_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[7]),
        .Q(masked_addr_q[7]),
        .R(SR));
  FDRE \masked_addr_q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[8]),
        .Q(masked_addr_q[8]),
        .R(SR));
  FDRE \masked_addr_q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[9]),
        .Q(masked_addr_q[9]),
        .R(SR));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry_n_0,next_mi_addr0_carry_n_1,next_mi_addr0_carry_n_2,next_mi_addr0_carry_n_3,next_mi_addr0_carry_n_4,next_mi_addr0_carry_n_5,next_mi_addr0_carry_n_6,next_mi_addr0_carry_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,pre_mi_addr__0[12],1'b0}),
        .O({next_mi_addr0_carry_n_8,next_mi_addr0_carry_n_9,next_mi_addr0_carry_n_10,next_mi_addr0_carry_n_11,next_mi_addr0_carry_n_12,next_mi_addr0_carry_n_13,next_mi_addr0_carry_n_14,next_mi_addr0_carry_n_15}),
        .S({pre_mi_addr__0[18:13],next_mi_addr0_carry_i_8__0_n_0,pre_mi_addr__0[11]}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__0
       (.CI(next_mi_addr0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__0_n_0,next_mi_addr0_carry__0_n_1,next_mi_addr0_carry__0_n_2,next_mi_addr0_carry__0_n_3,next_mi_addr0_carry__0_n_4,next_mi_addr0_carry__0_n_5,next_mi_addr0_carry__0_n_6,next_mi_addr0_carry__0_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__0_n_8,next_mi_addr0_carry__0_n_9,next_mi_addr0_carry__0_n_10,next_mi_addr0_carry__0_n_11,next_mi_addr0_carry__0_n_12,next_mi_addr0_carry__0_n_13,next_mi_addr0_carry__0_n_14,next_mi_addr0_carry__0_n_15}),
        .S(pre_mi_addr__0[26:19]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[26]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[26]),
        .O(pre_mi_addr__0[26]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[25]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[25]),
        .O(pre_mi_addr__0[25]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[24]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[24]),
        .O(pre_mi_addr__0[24]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[23]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[23]),
        .O(pre_mi_addr__0[23]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[22]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[22]),
        .O(pre_mi_addr__0[22]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[21]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[21]),
        .O(pre_mi_addr__0[21]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[20]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[20]),
        .O(pre_mi_addr__0[20]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_8__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[19]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[19]),
        .O(pre_mi_addr__0[19]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__1
       (.CI(next_mi_addr0_carry__0_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__1_n_0,next_mi_addr0_carry__1_n_1,next_mi_addr0_carry__1_n_2,next_mi_addr0_carry__1_n_3,next_mi_addr0_carry__1_n_4,next_mi_addr0_carry__1_n_5,next_mi_addr0_carry__1_n_6,next_mi_addr0_carry__1_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__1_n_8,next_mi_addr0_carry__1_n_9,next_mi_addr0_carry__1_n_10,next_mi_addr0_carry__1_n_11,next_mi_addr0_carry__1_n_12,next_mi_addr0_carry__1_n_13,next_mi_addr0_carry__1_n_14,next_mi_addr0_carry__1_n_15}),
        .S(pre_mi_addr__0[34:27]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[34]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[34]),
        .O(pre_mi_addr__0[34]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[33]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[33]),
        .O(pre_mi_addr__0[33]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[32]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[32]),
        .O(pre_mi_addr__0[32]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[31]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[31]),
        .O(pre_mi_addr__0[31]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[30]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[30]),
        .O(pre_mi_addr__0[30]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[29]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[29]),
        .O(pre_mi_addr__0[29]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[28]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[28]),
        .O(pre_mi_addr__0[28]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_8__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[27]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[27]),
        .O(pre_mi_addr__0[27]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__2
       (.CI(next_mi_addr0_carry__1_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__2_n_0,next_mi_addr0_carry__2_n_1,next_mi_addr0_carry__2_n_2,next_mi_addr0_carry__2_n_3,next_mi_addr0_carry__2_n_4,next_mi_addr0_carry__2_n_5,next_mi_addr0_carry__2_n_6,next_mi_addr0_carry__2_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__2_n_8,next_mi_addr0_carry__2_n_9,next_mi_addr0_carry__2_n_10,next_mi_addr0_carry__2_n_11,next_mi_addr0_carry__2_n_12,next_mi_addr0_carry__2_n_13,next_mi_addr0_carry__2_n_14,next_mi_addr0_carry__2_n_15}),
        .S(pre_mi_addr__0[42:35]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[42] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[42]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[42]),
        .O(pre_mi_addr__0[42]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[41] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[41]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[41]),
        .O(pre_mi_addr__0[41]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[40] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[40]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[40]),
        .O(pre_mi_addr__0[40]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[39]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[39]),
        .O(pre_mi_addr__0[39]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[38]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[38]),
        .O(pre_mi_addr__0[38]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[37]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[37]),
        .O(pre_mi_addr__0[37]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[36]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[36]),
        .O(pre_mi_addr__0[36]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_8__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[35]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[35]),
        .O(pre_mi_addr__0[35]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__3
       (.CI(next_mi_addr0_carry__2_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__3_n_0,next_mi_addr0_carry__3_n_1,next_mi_addr0_carry__3_n_2,next_mi_addr0_carry__3_n_3,next_mi_addr0_carry__3_n_4,next_mi_addr0_carry__3_n_5,next_mi_addr0_carry__3_n_6,next_mi_addr0_carry__3_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__3_n_8,next_mi_addr0_carry__3_n_9,next_mi_addr0_carry__3_n_10,next_mi_addr0_carry__3_n_11,next_mi_addr0_carry__3_n_12,next_mi_addr0_carry__3_n_13,next_mi_addr0_carry__3_n_14,next_mi_addr0_carry__3_n_15}),
        .S(pre_mi_addr__0[50:43]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[50] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[50]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[50]),
        .O(pre_mi_addr__0[50]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[49] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[49]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[49]),
        .O(pre_mi_addr__0[49]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[48] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[48]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[48]),
        .O(pre_mi_addr__0[48]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[47] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[47]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[47]),
        .O(pre_mi_addr__0[47]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[46] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[46]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[46]),
        .O(pre_mi_addr__0[46]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[45] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[45]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[45]),
        .O(pre_mi_addr__0[45]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[44] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[44]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[44]),
        .O(pre_mi_addr__0[44]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__3_i_8__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[43] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[43]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[43]),
        .O(pre_mi_addr__0[43]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__4
       (.CI(next_mi_addr0_carry__3_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__4_n_0,next_mi_addr0_carry__4_n_1,next_mi_addr0_carry__4_n_2,next_mi_addr0_carry__4_n_3,next_mi_addr0_carry__4_n_4,next_mi_addr0_carry__4_n_5,next_mi_addr0_carry__4_n_6,next_mi_addr0_carry__4_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__4_n_8,next_mi_addr0_carry__4_n_9,next_mi_addr0_carry__4_n_10,next_mi_addr0_carry__4_n_11,next_mi_addr0_carry__4_n_12,next_mi_addr0_carry__4_n_13,next_mi_addr0_carry__4_n_14,next_mi_addr0_carry__4_n_15}),
        .S(pre_mi_addr__0[58:51]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[58] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[58]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[58]),
        .O(pre_mi_addr__0[58]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[57] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[57]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[57]),
        .O(pre_mi_addr__0[57]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[56] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[56]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[56]),
        .O(pre_mi_addr__0[56]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[55] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[55]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[55]),
        .O(pre_mi_addr__0[55]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[54] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[54]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[54]),
        .O(pre_mi_addr__0[54]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[53] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[53]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[53]),
        .O(pre_mi_addr__0[53]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[52] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[52]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[52]),
        .O(pre_mi_addr__0[52]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__4_i_8__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[51] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[51]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[51]),
        .O(pre_mi_addr__0[51]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__5
       (.CI(next_mi_addr0_carry__4_n_0),
        .CI_TOP(1'b0),
        .CO({NLW_next_mi_addr0_carry__5_CO_UNCONNECTED[7:4],next_mi_addr0_carry__5_n_4,next_mi_addr0_carry__5_n_5,next_mi_addr0_carry__5_n_6,next_mi_addr0_carry__5_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({NLW_next_mi_addr0_carry__5_O_UNCONNECTED[7:5],next_mi_addr0_carry__5_n_11,next_mi_addr0_carry__5_n_12,next_mi_addr0_carry__5_n_13,next_mi_addr0_carry__5_n_14,next_mi_addr0_carry__5_n_15}),
        .S({1'b0,1'b0,1'b0,pre_mi_addr__0[63:59]}));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[63] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[63]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[63]),
        .O(pre_mi_addr__0[63]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[62] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[62]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[62]),
        .O(pre_mi_addr__0[62]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[61] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[61]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[61]),
        .O(pre_mi_addr__0[61]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[60] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[60]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[60]),
        .O(pre_mi_addr__0[60]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__5_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[59] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[59]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[59]),
        .O(pre_mi_addr__0[59]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[12]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[12]),
        .O(pre_mi_addr__0[12]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[18]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[18]),
        .O(pre_mi_addr__0[18]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[17]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[17]),
        .O(pre_mi_addr__0[17]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[16]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[16]),
        .O(pre_mi_addr__0[16]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[15]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[15]),
        .O(pre_mi_addr__0[15]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[14]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[14]),
        .O(pre_mi_addr__0[14]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[13]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[13]),
        .O(pre_mi_addr__0[13]));
  LUT6 #(
    .INIT(64'h47444777FFFFFFFF)) 
    next_mi_addr0_carry_i_8__0
       (.I0(next_mi_addr[12]),
        .I1(cmd_queue_n_304),
        .I2(masked_addr_q[12]),
        .I3(cmd_queue_n_305),
        .I4(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .I5(\split_addr_mask_q_reg_n_0_[12] ),
        .O(next_mi_addr0_carry_i_8__0_n_0));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_9__0
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[11]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[11]),
        .O(pre_mi_addr__0[11]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[10]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[10]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[10]),
        .O(pre_mi_addr[10]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[4]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[4] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[4]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[4]),
        .O(pre_mi_addr[4]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[5]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[5] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[5]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[5]),
        .O(pre_mi_addr[5]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[6]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[6] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[6]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[6]),
        .O(pre_mi_addr[6]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[7]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[7]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[7]),
        .O(pre_mi_addr[7]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[8]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[8]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[8]),
        .O(pre_mi_addr[8]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[9]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[12] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .I2(cmd_queue_n_305),
        .I3(masked_addr_q[9]),
        .I4(cmd_queue_n_304),
        .I5(next_mi_addr[9]),
        .O(pre_mi_addr[9]));
  FDRE \next_mi_addr_reg[10] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[10]),
        .Q(next_mi_addr[10]),
        .R(SR));
  FDRE \next_mi_addr_reg[11] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_15),
        .Q(next_mi_addr[11]),
        .R(SR));
  FDRE \next_mi_addr_reg[12] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_14),
        .Q(next_mi_addr[12]),
        .R(SR));
  FDRE \next_mi_addr_reg[13] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_13),
        .Q(next_mi_addr[13]),
        .R(SR));
  FDRE \next_mi_addr_reg[14] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_12),
        .Q(next_mi_addr[14]),
        .R(SR));
  FDRE \next_mi_addr_reg[15] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_11),
        .Q(next_mi_addr[15]),
        .R(SR));
  FDRE \next_mi_addr_reg[16] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_10),
        .Q(next_mi_addr[16]),
        .R(SR));
  FDRE \next_mi_addr_reg[17] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_9),
        .Q(next_mi_addr[17]),
        .R(SR));
  FDRE \next_mi_addr_reg[18] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_8),
        .Q(next_mi_addr[18]),
        .R(SR));
  FDRE \next_mi_addr_reg[19] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_15),
        .Q(next_mi_addr[19]),
        .R(SR));
  FDRE \next_mi_addr_reg[20] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_14),
        .Q(next_mi_addr[20]),
        .R(SR));
  FDRE \next_mi_addr_reg[21] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_13),
        .Q(next_mi_addr[21]),
        .R(SR));
  FDRE \next_mi_addr_reg[22] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_12),
        .Q(next_mi_addr[22]),
        .R(SR));
  FDRE \next_mi_addr_reg[23] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_11),
        .Q(next_mi_addr[23]),
        .R(SR));
  FDRE \next_mi_addr_reg[24] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_10),
        .Q(next_mi_addr[24]),
        .R(SR));
  FDRE \next_mi_addr_reg[25] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_9),
        .Q(next_mi_addr[25]),
        .R(SR));
  FDRE \next_mi_addr_reg[26] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_8),
        .Q(next_mi_addr[26]),
        .R(SR));
  FDRE \next_mi_addr_reg[27] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_15),
        .Q(next_mi_addr[27]),
        .R(SR));
  FDRE \next_mi_addr_reg[28] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_14),
        .Q(next_mi_addr[28]),
        .R(SR));
  FDRE \next_mi_addr_reg[29] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_13),
        .Q(next_mi_addr[29]),
        .R(SR));
  FDRE \next_mi_addr_reg[30] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_12),
        .Q(next_mi_addr[30]),
        .R(SR));
  FDRE \next_mi_addr_reg[31] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_11),
        .Q(next_mi_addr[31]),
        .R(SR));
  FDRE \next_mi_addr_reg[32] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_10),
        .Q(next_mi_addr[32]),
        .R(SR));
  FDRE \next_mi_addr_reg[33] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_9),
        .Q(next_mi_addr[33]),
        .R(SR));
  FDRE \next_mi_addr_reg[34] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_8),
        .Q(next_mi_addr[34]),
        .R(SR));
  FDRE \next_mi_addr_reg[35] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_15),
        .Q(next_mi_addr[35]),
        .R(SR));
  FDRE \next_mi_addr_reg[36] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_14),
        .Q(next_mi_addr[36]),
        .R(SR));
  FDRE \next_mi_addr_reg[37] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_13),
        .Q(next_mi_addr[37]),
        .R(SR));
  FDRE \next_mi_addr_reg[38] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_12),
        .Q(next_mi_addr[38]),
        .R(SR));
  FDRE \next_mi_addr_reg[39] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_11),
        .Q(next_mi_addr[39]),
        .R(SR));
  FDRE \next_mi_addr_reg[40] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_10),
        .Q(next_mi_addr[40]),
        .R(SR));
  FDRE \next_mi_addr_reg[41] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_9),
        .Q(next_mi_addr[41]),
        .R(SR));
  FDRE \next_mi_addr_reg[42] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_8),
        .Q(next_mi_addr[42]),
        .R(SR));
  FDRE \next_mi_addr_reg[43] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_15),
        .Q(next_mi_addr[43]),
        .R(SR));
  FDRE \next_mi_addr_reg[44] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_14),
        .Q(next_mi_addr[44]),
        .R(SR));
  FDRE \next_mi_addr_reg[45] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_13),
        .Q(next_mi_addr[45]),
        .R(SR));
  FDRE \next_mi_addr_reg[46] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_12),
        .Q(next_mi_addr[46]),
        .R(SR));
  FDRE \next_mi_addr_reg[47] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_11),
        .Q(next_mi_addr[47]),
        .R(SR));
  FDRE \next_mi_addr_reg[48] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_10),
        .Q(next_mi_addr[48]),
        .R(SR));
  FDRE \next_mi_addr_reg[49] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_9),
        .Q(next_mi_addr[49]),
        .R(SR));
  FDRE \next_mi_addr_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[4]),
        .Q(next_mi_addr[4]),
        .R(SR));
  FDRE \next_mi_addr_reg[50] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__3_n_8),
        .Q(next_mi_addr[50]),
        .R(SR));
  FDRE \next_mi_addr_reg[51] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_15),
        .Q(next_mi_addr[51]),
        .R(SR));
  FDRE \next_mi_addr_reg[52] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_14),
        .Q(next_mi_addr[52]),
        .R(SR));
  FDRE \next_mi_addr_reg[53] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_13),
        .Q(next_mi_addr[53]),
        .R(SR));
  FDRE \next_mi_addr_reg[54] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_12),
        .Q(next_mi_addr[54]),
        .R(SR));
  FDRE \next_mi_addr_reg[55] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_11),
        .Q(next_mi_addr[55]),
        .R(SR));
  FDRE \next_mi_addr_reg[56] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_10),
        .Q(next_mi_addr[56]),
        .R(SR));
  FDRE \next_mi_addr_reg[57] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_9),
        .Q(next_mi_addr[57]),
        .R(SR));
  FDRE \next_mi_addr_reg[58] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__4_n_8),
        .Q(next_mi_addr[58]),
        .R(SR));
  FDRE \next_mi_addr_reg[59] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_15),
        .Q(next_mi_addr[59]),
        .R(SR));
  FDRE \next_mi_addr_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[5]),
        .Q(next_mi_addr[5]),
        .R(SR));
  FDRE \next_mi_addr_reg[60] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_14),
        .Q(next_mi_addr[60]),
        .R(SR));
  FDRE \next_mi_addr_reg[61] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_13),
        .Q(next_mi_addr[61]),
        .R(SR));
  FDRE \next_mi_addr_reg[62] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_12),
        .Q(next_mi_addr[62]),
        .R(SR));
  FDRE \next_mi_addr_reg[63] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__5_n_11),
        .Q(next_mi_addr[63]),
        .R(SR));
  FDRE \next_mi_addr_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[6]),
        .Q(next_mi_addr[6]),
        .R(SR));
  FDRE \next_mi_addr_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[7]),
        .Q(next_mi_addr[7]),
        .R(SR));
  FDRE \next_mi_addr_reg[8] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[8]),
        .Q(next_mi_addr[8]),
        .R(SR));
  FDRE \next_mi_addr_reg[9] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[9]),
        .Q(next_mi_addr[9]),
        .R(SR));
  LUT6 #(
    .INIT(64'hF8A8580800000000)) 
    \num_transactions_q[0]_i_1__0 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arlen[7]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[6]),
        .I4(s_axi_arlen[5]),
        .I5(s_axi_arsize[2]),
        .O(\num_transactions_q[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h88800080)) 
    \num_transactions_q[1]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[6]),
        .O(num_transactions[1]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \num_transactions_q[2]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[7]),
        .O(num_transactions[2]));
  FDRE \num_transactions_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\num_transactions_q[0]_i_1__0_n_0 ),
        .Q(num_transactions_q[0]),
        .R(SR));
  FDRE \num_transactions_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[1]),
        .Q(num_transactions_q[1]),
        .R(SR));
  FDRE \num_transactions_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[2]),
        .Q(num_transactions_q[2]),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \pushed_commands[0]_i_1__0 
       (.I0(pushed_commands_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[1]_i_1__0 
       (.I0(pushed_commands_reg[0]),
        .I1(pushed_commands_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[2]_i_1__0 
       (.I0(pushed_commands_reg[2]),
        .I1(pushed_commands_reg[1]),
        .I2(pushed_commands_reg[0]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \pushed_commands[3]_i_1__0 
       (.I0(pushed_commands_reg[3]),
        .I1(pushed_commands_reg[0]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[2]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \pushed_commands[4]_i_1__0 
       (.I0(pushed_commands_reg[4]),
        .I1(pushed_commands_reg[3]),
        .I2(pushed_commands_reg[2]),
        .I3(pushed_commands_reg[1]),
        .I4(pushed_commands_reg[0]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \pushed_commands[5]_i_1__0 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[0]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[2]),
        .I4(pushed_commands_reg[3]),
        .I5(pushed_commands_reg[4]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[6]_i_1__0 
       (.I0(pushed_commands_reg[6]),
        .I1(\pushed_commands[7]_i_3__0_n_0 ),
        .O(p_0_in__0[6]));
  LUT2 #(
    .INIT(4'hB)) 
    \pushed_commands[7]_i_1__0 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(out),
        .O(\pushed_commands[7]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[7]_i_2__0 
       (.I0(pushed_commands_reg[7]),
        .I1(\pushed_commands[7]_i_3__0_n_0 ),
        .I2(pushed_commands_reg[6]),
        .O(p_0_in__0[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \pushed_commands[7]_i_3__0 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[0]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[2]),
        .I4(pushed_commands_reg[3]),
        .I5(pushed_commands_reg[4]),
        .O(\pushed_commands[7]_i_3__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[0] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[0]),
        .Q(pushed_commands_reg[0]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[1] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[1]),
        .Q(pushed_commands_reg[1]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[2] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[2]),
        .Q(pushed_commands_reg[2]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[3] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[3]),
        .Q(pushed_commands_reg[3]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[4]),
        .Q(pushed_commands_reg[4]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[5]),
        .Q(pushed_commands_reg[5]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[6]),
        .Q(pushed_commands_reg[6]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[7]),
        .Q(pushed_commands_reg[7]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE \queue_id_reg[0] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[0]),
        .Q(s_axi_rid[0]),
        .R(SR));
  FDRE \queue_id_reg[1] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[1]),
        .Q(s_axi_rid[1]),
        .R(SR));
  FDRE \queue_id_reg[2] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[2]),
        .Q(s_axi_rid[2]),
        .R(SR));
  FDRE \queue_id_reg[3] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[3]),
        .Q(s_axi_rid[3]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'h08)) 
    si_full_size_q_i_1__0
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[1]),
        .O(si_full_size));
  FDRE #(
    .INIT(1'b0)) 
    si_full_size_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(si_full_size),
        .Q(si_full_size_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \split_addr_mask_q[0]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .O(split_addr_mask[0]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \split_addr_mask_q[1]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .O(split_addr_mask[1]));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \split_addr_mask_q[2]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .O(\split_addr_mask_q[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \split_addr_mask_q[3]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .O(split_addr_mask[3]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'h37)) 
    \split_addr_mask_q[4]_i_1__0 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .O(split_addr_mask[4]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \split_addr_mask_q[5]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .O(split_addr_mask[5]));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \split_addr_mask_q[6]_i_1 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .O(split_addr_mask[6]));
  FDRE \split_addr_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[0]),
        .Q(\split_addr_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(1'b1),
        .Q(\split_addr_mask_q_reg_n_0_[12] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[1]),
        .Q(\split_addr_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\split_addr_mask_q[2]_i_1__0_n_0 ),
        .Q(\split_addr_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[3]),
        .Q(\split_addr_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[4]),
        .Q(\split_addr_mask_q_reg_n_0_[4] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[5]),
        .Q(\split_addr_mask_q_reg_n_0_[5] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[6]),
        .Q(\split_addr_mask_q_reg_n_0_[6] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    split_ongoing_reg
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(cmd_split_i),
        .Q(split_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT4 #(
    .INIT(16'hA080)) 
    \unalignment_addr_q[0]_i_1__0 
       (.I0(s_axi_araddr[4]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .O(unalignment_addr[0]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \unalignment_addr_q[1]_i_1__0 
       (.I0(s_axi_araddr[5]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .O(unalignment_addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \unalignment_addr_q[2]_i_1 
       (.I0(s_axi_araddr[6]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[2]),
        .O(unalignment_addr[2]));
  FDRE \unalignment_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[0]),
        .Q(unalignment_addr_q[0]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[1]),
        .Q(unalignment_addr_q[1]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[2]),
        .Q(unalignment_addr_q[2]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h000000E0)) 
    wrap_need_to_split_q_i_1__0
       (.I0(wrap_need_to_split_q_i_2__0_n_0),
        .I1(wrap_need_to_split_q_i_3__0_n_0),
        .I2(s_axi_arburst[1]),
        .I3(s_axi_arburst[0]),
        .I4(legal_wrap_len_q_i_1__0_n_0),
        .O(wrap_need_to_split));
  LUT6 #(
    .INIT(64'hFFFFFFF8FFF8FFF8)) 
    wrap_need_to_split_q_i_2__0
       (.I0(s_axi_araddr[10]),
        .I1(wrap_need_to_split_q_i_4__0_n_0),
        .I2(wrap_unaligned_len[7]),
        .I3(wrap_unaligned_len[4]),
        .I4(s_axi_araddr[9]),
        .I5(\masked_addr_q[9]_i_2__0_n_0 ),
        .O(wrap_need_to_split_q_i_2__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    wrap_need_to_split_q_i_3__0
       (.I0(s_axi_araddr[4]),
        .I1(cmd_mask_i[4]),
        .I2(s_axi_araddr[5]),
        .I3(\masked_addr_q[5]_i_2__0_n_0 ),
        .I4(wrap_unaligned_len[2]),
        .I5(wrap_unaligned_len[3]),
        .O(wrap_need_to_split_q_i_3__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'hB8888888)) 
    wrap_need_to_split_q_i_4__0
       (.I0(\masked_addr_q[10]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[7]),
        .I4(s_axi_arsize[1]),
        .O(wrap_need_to_split_q_i_4__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    wrap_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_need_to_split),
        .Q(wrap_need_to_split_q),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \wrap_rest_len[0]_i_1__0 
       (.I0(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[0]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrap_rest_len[1]_i_1__0 
       (.I0(wrap_unaligned_len_q[0]),
        .I1(wrap_unaligned_len_q[1]),
        .O(\wrap_rest_len[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wrap_rest_len[2]_i_1__0 
       (.I0(wrap_unaligned_len_q[2]),
        .I1(wrap_unaligned_len_q[1]),
        .I2(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[2]));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wrap_rest_len[3]_i_1__0 
       (.I0(wrap_unaligned_len_q[3]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .O(wrap_rest_len0[3]));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \wrap_rest_len[4]_i_1__0 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[3]),
        .I2(wrap_unaligned_len_q[1]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[2]),
        .O(wrap_rest_len0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \wrap_rest_len[5]_i_1__0 
       (.I0(wrap_unaligned_len_q[5]),
        .I1(wrap_unaligned_len_q[4]),
        .I2(wrap_unaligned_len_q[2]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[1]),
        .I5(wrap_unaligned_len_q[3]),
        .O(wrap_rest_len0[5]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wrap_rest_len[6]_i_1__0 
       (.I0(wrap_unaligned_len_q[6]),
        .I1(\wrap_rest_len[7]_i_2__0_n_0 ),
        .O(wrap_rest_len0[6]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wrap_rest_len[7]_i_1__0 
       (.I0(wrap_unaligned_len_q[7]),
        .I1(wrap_unaligned_len_q[6]),
        .I2(\wrap_rest_len[7]_i_2__0_n_0 ),
        .O(wrap_rest_len0[7]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wrap_rest_len[7]_i_2__0 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .I4(wrap_unaligned_len_q[3]),
        .I5(wrap_unaligned_len_q[5]),
        .O(\wrap_rest_len[7]_i_2__0_n_0 ));
  FDRE \wrap_rest_len_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[0]),
        .Q(wrap_rest_len[0]),
        .R(SR));
  FDRE \wrap_rest_len_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrap_rest_len[1]_i_1__0_n_0 ),
        .Q(wrap_rest_len[1]),
        .R(SR));
  FDRE \wrap_rest_len_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[2]),
        .Q(wrap_rest_len[2]),
        .R(SR));
  FDRE \wrap_rest_len_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[3]),
        .Q(wrap_rest_len[3]),
        .R(SR));
  FDRE \wrap_rest_len_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[4]),
        .Q(wrap_rest_len[4]),
        .R(SR));
  FDRE \wrap_rest_len_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[5]),
        .Q(wrap_rest_len[5]),
        .R(SR));
  FDRE \wrap_rest_len_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[6]),
        .Q(wrap_rest_len[6]),
        .R(SR));
  FDRE \wrap_rest_len_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[7]),
        .Q(wrap_rest_len[7]),
        .R(SR));
  LUT6 #(
    .INIT(64'hA8A8A8A8A8A8A808)) 
    \wrap_unaligned_len_q[0]_i_1__0 
       (.I0(s_axi_araddr[4]),
        .I1(\masked_addr_q[8]_i_2__0_n_0 ),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[0]),
        .I5(s_axi_arsize[1]),
        .O(wrap_unaligned_len[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[1]_i_1__0 
       (.I0(s_axi_araddr[5]),
        .I1(\masked_addr_q[5]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[1]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[2]_i_1__0 
       (.I0(\masked_addr_q[6]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[10]_i_2__0_n_0 ),
        .I3(s_axi_araddr[6]),
        .O(wrap_unaligned_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[3]_i_1__0 
       (.I0(\masked_addr_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[11]_i_2__0_n_0 ),
        .I3(s_axi_araddr[7]),
        .O(wrap_unaligned_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[4]_i_1__0 
       (.I0(\masked_addr_q[8]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[8]_i_3__0_n_0 ),
        .I3(s_axi_araddr[8]),
        .O(wrap_unaligned_len[4]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[5]_i_1__0 
       (.I0(s_axi_araddr[9]),
        .I1(\masked_addr_q[9]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[5]));
  LUT6 #(
    .INIT(64'hAAAA800000008000)) 
    \wrap_unaligned_len_q[6]_i_1__0 
       (.I0(s_axi_araddr[10]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arsize[2]),
        .I5(\masked_addr_q[10]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[6]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \wrap_unaligned_len_q[7]_i_1__0 
       (.I0(s_axi_araddr[11]),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[11]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[7]));
  FDRE \wrap_unaligned_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[0]),
        .Q(wrap_unaligned_len_q[0]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[1]),
        .Q(wrap_unaligned_len_q[1]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[2]),
        .Q(wrap_unaligned_len_q[2]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[3]),
        .Q(wrap_unaligned_len_q[3]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[4]),
        .Q(wrap_unaligned_len_q[4]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[5]),
        .Q(wrap_unaligned_len_q[5]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[6]),
        .Q(wrap_unaligned_len_q[6]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[7]),
        .Q(wrap_unaligned_len_q[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_27_axi_downsizer" *) 
module axi4_dwtrans_axi_dwidth_converter_v2_1_27_axi_downsizer
   (E,
    command_ongoing_reg,
    S_AXI_AREADY_I_reg,
    command_ongoing_reg_0,
    s_axi_rdata,
    s_axi_bresp,
    din,
    s_axi_bid,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    \goreg_dm.dout_i_reg[9] ,
    \S_AXI_ASIZE_Q_reg[2] ,
    s_axi_rid,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    s_axi_rresp,
    s_axi_bvalid,
    m_axi_bready,
    m_axi_awlock,
    m_axi_awaddr,
    m_axi_wvalid,
    s_axi_wready,
    m_axi_arlock,
    m_axi_araddr,
    s_axi_rvalid,
    m_axi_rready,
    m_axi_awburst,
    m_axi_wstrb,
    m_axi_wdata,
    m_axi_arburst,
    s_axi_rlast,
    s_axi_arsize,
    s_axi_awsize,
    s_axi_awlen,
    s_axi_arlen,
    s_axi_awvalid,
    m_axi_awready,
    out,
    s_axi_arvalid,
    m_axi_arready,
    s_axi_rready,
    m_axi_rvalid,
    m_axi_rdata,
    s_axi_awaddr,
    s_axi_araddr,
    CLK,
    s_axi_awid,
    s_axi_awburst,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos,
    s_axi_arid,
    s_axi_arburst,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos,
    m_axi_rlast,
    m_axi_bvalid,
    s_axi_bready,
    s_axi_wvalid,
    m_axi_wready,
    m_axi_rresp,
    m_axi_bresp,
    s_axi_wstrb,
    s_axi_wdata);
  output [0:0]E;
  output command_ongoing_reg;
  output [0:0]S_AXI_AREADY_I_reg;
  output command_ongoing_reg_0;
  output [255:0]s_axi_rdata;
  output [1:0]s_axi_bresp;
  output [10:0]din;
  output [3:0]s_axi_bid;
  output [3:0]m_axi_awcache;
  output [2:0]m_axi_awprot;
  output [3:0]m_axi_awregion;
  output [3:0]m_axi_awqos;
  output \goreg_dm.dout_i_reg[9] ;
  output [10:0]\S_AXI_ASIZE_Q_reg[2] ;
  output [3:0]s_axi_rid;
  output [3:0]m_axi_arcache;
  output [2:0]m_axi_arprot;
  output [3:0]m_axi_arregion;
  output [3:0]m_axi_arqos;
  output [1:0]s_axi_rresp;
  output s_axi_bvalid;
  output m_axi_bready;
  output [0:0]m_axi_awlock;
  output [63:0]m_axi_awaddr;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]m_axi_arlock;
  output [63:0]m_axi_araddr;
  output s_axi_rvalid;
  output m_axi_rready;
  output [1:0]m_axi_awburst;
  output [15:0]m_axi_wstrb;
  output [127:0]m_axi_wdata;
  output [1:0]m_axi_arburst;
  output s_axi_rlast;
  input [2:0]s_axi_arsize;
  input [2:0]s_axi_awsize;
  input [7:0]s_axi_awlen;
  input [7:0]s_axi_arlen;
  input s_axi_awvalid;
  input m_axi_awready;
  input out;
  input s_axi_arvalid;
  input m_axi_arready;
  input s_axi_rready;
  input m_axi_rvalid;
  input [127:0]m_axi_rdata;
  input [63:0]s_axi_awaddr;
  input [63:0]s_axi_araddr;
  input CLK;
  input [3:0]s_axi_awid;
  input [1:0]s_axi_awburst;
  input [0:0]s_axi_awlock;
  input [3:0]s_axi_awcache;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awregion;
  input [3:0]s_axi_awqos;
  input [3:0]s_axi_arid;
  input [1:0]s_axi_arburst;
  input [0:0]s_axi_arlock;
  input [3:0]s_axi_arcache;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arregion;
  input [3:0]s_axi_arqos;
  input m_axi_rlast;
  input m_axi_bvalid;
  input s_axi_bready;
  input s_axi_wvalid;
  input m_axi_wready;
  input [1:0]m_axi_rresp;
  input [1:0]m_axi_bresp;
  input [31:0]s_axi_wstrb;
  input [255:0]s_axi_wdata;

  wire CLK;
  wire [0:0]E;
  wire [0:0]S_AXI_AREADY_I_reg;
  wire [10:0]\S_AXI_ASIZE_Q_reg[2] ;
  wire S_AXI_RDATA_II;
  wire \USE_B_CHANNEL.cmd_b_queue/inst/empty ;
  wire [4:0]\USE_READ.rd_cmd_first_word ;
  wire \USE_READ.rd_cmd_fix ;
  wire [7:0]\USE_READ.rd_cmd_length ;
  wire \USE_READ.rd_cmd_mirror ;
  wire [2:0]\USE_READ.rd_cmd_size ;
  wire \USE_READ.read_addr_inst_n_33 ;
  wire \USE_READ.read_addr_inst_n_369 ;
  wire \USE_READ.read_data_inst_n_10 ;
  wire \USE_READ.read_data_inst_n_11 ;
  wire \USE_READ.read_data_inst_n_12 ;
  wire \USE_READ.read_data_inst_n_2 ;
  wire \USE_READ.read_data_inst_n_3 ;
  wire \USE_READ.read_data_inst_n_6 ;
  wire \USE_READ.read_data_inst_n_7 ;
  wire \USE_READ.read_data_inst_n_8 ;
  wire \USE_READ.read_data_inst_n_9 ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire [3:0]\USE_WRITE.wr_cmd_b_repeat ;
  wire \USE_WRITE.wr_cmd_b_split ;
  wire [4:0]\USE_WRITE.wr_cmd_first_word ;
  wire \USE_WRITE.wr_cmd_fix ;
  wire [7:0]\USE_WRITE.wr_cmd_length ;
  wire [4:0]\USE_WRITE.wr_cmd_offset ;
  wire \USE_WRITE.write_addr_inst_n_120 ;
  wire \USE_WRITE.write_addr_inst_n_6 ;
  wire \USE_WRITE.write_data_inst_n_146 ;
  wire \USE_WRITE.write_data_inst_n_147 ;
  wire \USE_WRITE.write_data_inst_n_150 ;
  wire \USE_WRITE.write_data_inst_n_151 ;
  wire \USE_WRITE.write_data_inst_n_152 ;
  wire \WORD_LANE[0].S_AXI_RDATA_II_reg0 ;
  wire \WORD_LANE[1].S_AXI_RDATA_II_reg0 ;
  wire [1:0]areset_d;
  wire [2:0]cmd_size_ii;
  wire command_ongoing_reg;
  wire command_ongoing_reg_0;
  wire [3:2]current_word_1;
  wire [10:0]din;
  wire first_mi_word;
  wire first_mi_word_1;
  wire \goreg_dm.dout_i_reg[9] ;
  wire [7:7]length_counter_1_reg;
  wire [63:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire [3:0]m_axi_arregion;
  wire [63:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [127:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire [1:0]m_axi_rresp;
  wire m_axi_rvalid;
  wire [127:0]m_axi_wdata;
  wire m_axi_wready;
  wire [15:0]m_axi_wstrb;
  wire m_axi_wvalid;
  wire out;
  wire [4:0]p_0_in;
  wire [4:0]p_0_in_0;
  wire [255:0]p_1_in;
  wire p_2_in;
  wire p_3_in;
  wire [63:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [3:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [63:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [3:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [3:0]s_axi_bid;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire [255:0]s_axi_rdata;
  wire [3:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire s_axi_rvalid;
  wire [255:0]s_axi_wdata;
  wire s_axi_wready;
  wire [31:0]s_axi_wstrb;
  wire s_axi_wvalid;

  axi4_dwtrans_axi_dwidth_converter_v2_1_27_a_downsizer__parameterized0 \USE_READ.read_addr_inst 
       (.CLK(CLK),
        .E(p_3_in),
        .Q(length_counter_1_reg),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .S_AXI_AREADY_I_reg_0(S_AXI_AREADY_I_reg),
        .S_AXI_AREADY_I_reg_1(\USE_WRITE.write_addr_inst_n_120 ),
        .\S_AXI_ASIZE_Q_reg[2]_0 (\S_AXI_ASIZE_Q_reg[2] ),
        .areset_d(areset_d),
        .\cmd_depth_reg[5]_0 (\USE_READ.read_data_inst_n_2 ),
        .command_ongoing_reg_0(command_ongoing_reg_0),
        .\current_word_1_reg[1] (\USE_READ.read_data_inst_n_8 ),
        .\current_word_1_reg[1]_0 (\USE_READ.read_data_inst_n_10 ),
        .\current_word_1_reg[2] (\USE_READ.read_data_inst_n_9 ),
        .\current_word_1_reg[3] (\USE_READ.read_data_inst_n_6 ),
        .\current_word_1_reg[3]_0 (\USE_READ.read_data_inst_n_12 ),
        .\current_word_1_reg[4] (\USE_READ.read_data_inst_n_11 ),
        .dout({\USE_READ.rd_cmd_fix ,\USE_READ.rd_cmd_mirror ,\USE_READ.rd_cmd_first_word ,cmd_size_ii,\USE_READ.rd_cmd_length ,\USE_READ.rd_cmd_size }),
        .empty_fwft_i_reg(\WORD_LANE[1].S_AXI_RDATA_II_reg0 ),
        .empty_fwft_i_reg_0(\WORD_LANE[0].S_AXI_RDATA_II_reg0 ),
        .first_mi_word(first_mi_word),
        .\goreg_dm.dout_i_reg[2] (\USE_READ.read_addr_inst_n_369 ),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arqos(m_axi_arqos),
        .m_axi_arready(m_axi_arready),
        .m_axi_arready_0(\USE_READ.read_addr_inst_n_33 ),
        .m_axi_arregion(m_axi_arregion),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rvalid(m_axi_rvalid),
        .out(out),
        .p_0_in(p_0_in),
        .p_1_in(p_1_in),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_aresetn(S_AXI_RDATA_II),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arregion(s_axi_arregion),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rdata_0_sp_1(\USE_READ.read_data_inst_n_7 ),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_rvalid_0(\USE_READ.read_data_inst_n_3 ));
  axi4_dwtrans_axi_dwidth_converter_v2_1_27_r_downsizer \USE_READ.read_data_inst 
       (.CLK(CLK),
        .D(p_0_in),
        .E(p_3_in),
        .Q(length_counter_1_reg),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .\S_AXI_RRESP_ACC_reg[1]_0 (\USE_READ.read_addr_inst_n_369 ),
        .\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 (S_AXI_RDATA_II),
        .\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 (\WORD_LANE[0].S_AXI_RDATA_II_reg0 ),
        .\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 (\WORD_LANE[1].S_AXI_RDATA_II_reg0 ),
        .\current_word_1_reg[0]_0 (\USE_READ.read_data_inst_n_8 ),
        .\current_word_1_reg[1]_0 (\USE_READ.read_data_inst_n_10 ),
        .\current_word_1_reg[2]_0 (\USE_READ.read_data_inst_n_9 ),
        .\current_word_1_reg[3]_0 (\USE_READ.read_data_inst_n_6 ),
        .\current_word_1_reg[4]_0 (\USE_READ.read_data_inst_n_7 ),
        .dout({\USE_READ.rd_cmd_fix ,\USE_READ.rd_cmd_mirror ,\USE_READ.rd_cmd_first_word ,cmd_size_ii,\USE_READ.rd_cmd_length ,\USE_READ.rd_cmd_size }),
        .first_mi_word(first_mi_word),
        .\goreg_dm.dout_i_reg[12] (\USE_READ.read_data_inst_n_12 ),
        .\goreg_dm.dout_i_reg[13] (\USE_READ.read_data_inst_n_11 ),
        .\goreg_dm.dout_i_reg[9] (\USE_READ.read_data_inst_n_2 ),
        .\length_counter_1_reg[4]_0 (\USE_READ.read_data_inst_n_3 ),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rresp(m_axi_rresp),
        .p_1_in(p_1_in),
        .s_axi_rresp(s_axi_rresp));
  axi4_dwtrans_axi_dwidth_converter_v2_1_27_b_downsizer \USE_WRITE.USE_SPLIT.write_resp_inst 
       (.CLK(CLK),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .dout({\USE_WRITE.wr_cmd_b_split ,\USE_WRITE.wr_cmd_b_repeat }),
        .empty(\USE_B_CHANNEL.cmd_b_queue/inst/empty ),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_bvalid(s_axi_bvalid));
  axi4_dwtrans_axi_dwidth_converter_v2_1_27_a_downsizer \USE_WRITE.write_addr_inst 
       (.CLK(CLK),
        .D(p_0_in_0),
        .E(p_2_in),
        .Q(current_word_1),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .S_AXI_AREADY_I_reg_0(E),
        .S_AXI_AREADY_I_reg_1(\USE_READ.read_addr_inst_n_33 ),
        .S_AXI_AREADY_I_reg_2(S_AXI_AREADY_I_reg),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .areset_d(areset_d),
        .\areset_d_reg[0]_0 (\USE_WRITE.write_addr_inst_n_120 ),
        .command_ongoing_reg_0(command_ongoing_reg),
        .\current_word_1[4]_i_2 (\USE_WRITE.write_data_inst_n_150 ),
        .\current_word_1_reg[1] (\USE_WRITE.write_data_inst_n_151 ),
        .\current_word_1_reg[1]_0 (\USE_WRITE.write_data_inst_n_152 ),
        .\current_word_1_reg[4] (\USE_WRITE.write_data_inst_n_147 ),
        .\current_word_1_reg[4]_0 (\USE_WRITE.write_data_inst_n_146 ),
        .din(din),
        .dout({\USE_WRITE.wr_cmd_b_split ,\USE_WRITE.wr_cmd_b_repeat }),
        .empty(\USE_B_CHANNEL.cmd_b_queue/inst/empty ),
        .first_mi_word(first_mi_word_1),
        .\goreg_dm.dout_i_reg[31] ({\USE_WRITE.wr_cmd_fix ,\USE_WRITE.wr_cmd_first_word ,\USE_WRITE.wr_cmd_offset ,\USE_WRITE.wr_cmd_length }),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awqos(m_axi_awqos),
        .m_axi_awready(m_axi_awready),
        .m_axi_awregion(m_axi_awregion),
        .m_axi_wready(m_axi_wready),
        .m_axi_wvalid(m_axi_wvalid),
        .out(out),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awregion(s_axi_awregion),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bid(s_axi_bid),
        .s_axi_wready(s_axi_wready),
        .s_axi_wready_0(\goreg_dm.dout_i_reg[9] ),
        .s_axi_wvalid(s_axi_wvalid));
  axi4_dwtrans_axi_dwidth_converter_v2_1_27_w_downsizer \USE_WRITE.write_data_inst 
       (.CLK(CLK),
        .D(p_0_in_0),
        .E(p_2_in),
        .Q(current_word_1),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .\current_word_1_reg[0]_0 (\USE_WRITE.write_data_inst_n_152 ),
        .\current_word_1_reg[1]_0 (\USE_WRITE.write_data_inst_n_151 ),
        .\current_word_1_reg[1]_1 ({\USE_WRITE.wr_cmd_fix ,\USE_WRITE.wr_cmd_first_word ,\USE_WRITE.wr_cmd_offset ,\USE_WRITE.wr_cmd_length }),
        .\current_word_1_reg[2]_0 (\USE_WRITE.write_data_inst_n_150 ),
        .\current_word_1_reg[3]_0 (\USE_WRITE.write_data_inst_n_146 ),
        .\current_word_1_reg[4]_0 (\USE_WRITE.write_data_inst_n_147 ),
        .first_mi_word(first_mi_word_1),
        .\goreg_dm.dout_i_reg[9] (\goreg_dm.dout_i_reg[9] ),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wstrb(m_axi_wstrb),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wstrb(s_axi_wstrb));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_27_b_downsizer" *) 
module axi4_dwtrans_axi_dwidth_converter_v2_1_27_b_downsizer
   (\USE_WRITE.wr_cmd_b_ready ,
    s_axi_bvalid,
    m_axi_bready,
    s_axi_bresp,
    SR,
    CLK,
    dout,
    m_axi_bvalid,
    s_axi_bready,
    empty,
    m_axi_bresp);
  output \USE_WRITE.wr_cmd_b_ready ;
  output s_axi_bvalid;
  output m_axi_bready;
  output [1:0]s_axi_bresp;
  input [0:0]SR;
  input CLK;
  input [4:0]dout;
  input m_axi_bvalid;
  input s_axi_bready;
  input empty;
  input [1:0]m_axi_bresp;

  wire CLK;
  wire [0:0]SR;
  wire [1:0]S_AXI_BRESP_ACC;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire [4:0]dout;
  wire empty;
  wire first_mi_word;
  wire last_word;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [7:0]next_repeat_cnt;
  wire p_1_in;
  wire \repeat_cnt[1]_i_1_n_0 ;
  wire \repeat_cnt[2]_i_2_n_0 ;
  wire \repeat_cnt[3]_i_2_n_0 ;
  wire \repeat_cnt[5]_i_2_n_0 ;
  wire \repeat_cnt[7]_i_2_n_0 ;
  wire [7:0]repeat_cnt_reg;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire s_axi_bvalid_INST_0_i_1_n_0;
  wire s_axi_bvalid_INST_0_i_2_n_0;

  FDRE \S_AXI_BRESP_ACC_reg[0] 
       (.C(CLK),
        .CE(p_1_in),
        .D(s_axi_bresp[0]),
        .Q(S_AXI_BRESP_ACC[0]),
        .R(SR));
  FDRE \S_AXI_BRESP_ACC_reg[1] 
       (.C(CLK),
        .CE(p_1_in),
        .D(s_axi_bresp[1]),
        .Q(S_AXI_BRESP_ACC[1]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    fifo_gen_inst_i_7
       (.I0(s_axi_bvalid_INST_0_i_1_n_0),
        .I1(m_axi_bvalid),
        .I2(s_axi_bready),
        .I3(empty),
        .O(\USE_WRITE.wr_cmd_b_ready ));
  LUT3 #(
    .INIT(8'hA8)) 
    first_mi_word_i_1
       (.I0(m_axi_bvalid),
        .I1(s_axi_bvalid_INST_0_i_1_n_0),
        .I2(s_axi_bready),
        .O(p_1_in));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT1 #(
    .INIT(2'h1)) 
    first_mi_word_i_2
       (.I0(s_axi_bvalid_INST_0_i_1_n_0),
        .O(last_word));
  FDSE first_mi_word_reg
       (.C(CLK),
        .CE(p_1_in),
        .D(last_word),
        .Q(first_mi_word),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'hE)) 
    m_axi_bready_INST_0
       (.I0(s_axi_bvalid_INST_0_i_1_n_0),
        .I1(s_axi_bready),
        .O(m_axi_bready));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'h1D)) 
    \repeat_cnt[0]_i_1 
       (.I0(repeat_cnt_reg[0]),
        .I1(first_mi_word),
        .I2(dout[0]),
        .O(next_repeat_cnt[0]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT5 #(
    .INIT(32'hCCA533A5)) 
    \repeat_cnt[1]_i_1 
       (.I0(repeat_cnt_reg[1]),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[0]),
        .I3(first_mi_word),
        .I4(dout[0]),
        .O(\repeat_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEFA051111FA05)) 
    \repeat_cnt[2]_i_1 
       (.I0(\repeat_cnt[2]_i_2_n_0 ),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[1]),
        .I3(repeat_cnt_reg[2]),
        .I4(first_mi_word),
        .I5(dout[2]),
        .O(next_repeat_cnt[2]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \repeat_cnt[2]_i_2 
       (.I0(dout[0]),
        .I1(first_mi_word),
        .I2(repeat_cnt_reg[0]),
        .O(\repeat_cnt[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \repeat_cnt[3]_i_1 
       (.I0(dout[2]),
        .I1(repeat_cnt_reg[2]),
        .I2(\repeat_cnt[3]_i_2_n_0 ),
        .I3(repeat_cnt_reg[3]),
        .I4(first_mi_word),
        .I5(dout[3]),
        .O(next_repeat_cnt[3]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT5 #(
    .INIT(32'h00053305)) 
    \repeat_cnt[3]_i_2 
       (.I0(repeat_cnt_reg[1]),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[0]),
        .I3(first_mi_word),
        .I4(dout[0]),
        .O(\repeat_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h3A350A0A)) 
    \repeat_cnt[4]_i_1 
       (.I0(repeat_cnt_reg[4]),
        .I1(dout[3]),
        .I2(first_mi_word),
        .I3(repeat_cnt_reg[3]),
        .I4(\repeat_cnt[5]_i_2_n_0 ),
        .O(next_repeat_cnt[4]));
  LUT6 #(
    .INIT(64'h0A0A090AFA0AF90A)) 
    \repeat_cnt[5]_i_1 
       (.I0(repeat_cnt_reg[5]),
        .I1(repeat_cnt_reg[4]),
        .I2(first_mi_word),
        .I3(\repeat_cnt[5]_i_2_n_0 ),
        .I4(repeat_cnt_reg[3]),
        .I5(dout[3]),
        .O(next_repeat_cnt[5]));
  LUT6 #(
    .INIT(64'h0000000511110005)) 
    \repeat_cnt[5]_i_2 
       (.I0(\repeat_cnt[2]_i_2_n_0 ),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[1]),
        .I3(repeat_cnt_reg[2]),
        .I4(first_mi_word),
        .I5(dout[2]),
        .O(\repeat_cnt[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFA0AF90A)) 
    \repeat_cnt[6]_i_1 
       (.I0(repeat_cnt_reg[6]),
        .I1(repeat_cnt_reg[5]),
        .I2(first_mi_word),
        .I3(\repeat_cnt[7]_i_2_n_0 ),
        .I4(repeat_cnt_reg[4]),
        .O(next_repeat_cnt[6]));
  LUT6 #(
    .INIT(64'hFAFA0A0AFAF90A0A)) 
    \repeat_cnt[7]_i_1 
       (.I0(repeat_cnt_reg[7]),
        .I1(repeat_cnt_reg[6]),
        .I2(first_mi_word),
        .I3(repeat_cnt_reg[4]),
        .I4(\repeat_cnt[7]_i_2_n_0 ),
        .I5(repeat_cnt_reg[5]),
        .O(next_repeat_cnt[7]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \repeat_cnt[7]_i_2 
       (.I0(dout[2]),
        .I1(repeat_cnt_reg[2]),
        .I2(\repeat_cnt[3]_i_2_n_0 ),
        .I3(repeat_cnt_reg[3]),
        .I4(first_mi_word),
        .I5(dout[3]),
        .O(\repeat_cnt[7]_i_2_n_0 ));
  FDRE \repeat_cnt_reg[0] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[0]),
        .Q(repeat_cnt_reg[0]),
        .R(SR));
  FDRE \repeat_cnt_reg[1] 
       (.C(CLK),
        .CE(p_1_in),
        .D(\repeat_cnt[1]_i_1_n_0 ),
        .Q(repeat_cnt_reg[1]),
        .R(SR));
  FDRE \repeat_cnt_reg[2] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[2]),
        .Q(repeat_cnt_reg[2]),
        .R(SR));
  FDRE \repeat_cnt_reg[3] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[3]),
        .Q(repeat_cnt_reg[3]),
        .R(SR));
  FDRE \repeat_cnt_reg[4] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[4]),
        .Q(repeat_cnt_reg[4]),
        .R(SR));
  FDRE \repeat_cnt_reg[5] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[5]),
        .Q(repeat_cnt_reg[5]),
        .R(SR));
  FDRE \repeat_cnt_reg[6] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[6]),
        .Q(repeat_cnt_reg[6]),
        .R(SR));
  FDRE \repeat_cnt_reg[7] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[7]),
        .Q(repeat_cnt_reg[7]),
        .R(SR));
  LUT6 #(
    .INIT(64'hAAAAAAAAECAEAAAA)) 
    \s_axi_bresp[0]_INST_0 
       (.I0(m_axi_bresp[0]),
        .I1(S_AXI_BRESP_ACC[0]),
        .I2(m_axi_bresp[1]),
        .I3(S_AXI_BRESP_ACC[1]),
        .I4(dout[4]),
        .I5(first_mi_word),
        .O(s_axi_bresp[0]));
  LUT4 #(
    .INIT(16'hAEAA)) 
    \s_axi_bresp[1]_INST_0 
       (.I0(m_axi_bresp[1]),
        .I1(dout[4]),
        .I2(first_mi_word),
        .I3(S_AXI_BRESP_ACC[1]),
        .O(s_axi_bresp[1]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT2 #(
    .INIT(4'h2)) 
    s_axi_bvalid_INST_0
       (.I0(m_axi_bvalid),
        .I1(s_axi_bvalid_INST_0_i_1_n_0),
        .O(s_axi_bvalid));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    s_axi_bvalid_INST_0_i_1
       (.I0(dout[4]),
        .I1(s_axi_bvalid_INST_0_i_2_n_0),
        .I2(repeat_cnt_reg[6]),
        .I3(repeat_cnt_reg[7]),
        .I4(repeat_cnt_reg[5]),
        .O(s_axi_bvalid_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    s_axi_bvalid_INST_0_i_2
       (.I0(repeat_cnt_reg[3]),
        .I1(first_mi_word),
        .I2(repeat_cnt_reg[0]),
        .I3(repeat_cnt_reg[4]),
        .I4(repeat_cnt_reg[1]),
        .I5(repeat_cnt_reg[2]),
        .O(s_axi_bvalid_INST_0_i_2_n_0));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_27_r_downsizer" *) 
module axi4_dwtrans_axi_dwidth_converter_v2_1_27_r_downsizer
   (first_mi_word,
    Q,
    \goreg_dm.dout_i_reg[9] ,
    \length_counter_1_reg[4]_0 ,
    s_axi_rresp,
    \current_word_1_reg[3]_0 ,
    \current_word_1_reg[4]_0 ,
    \current_word_1_reg[0]_0 ,
    \current_word_1_reg[2]_0 ,
    \current_word_1_reg[1]_0 ,
    \goreg_dm.dout_i_reg[13] ,
    \goreg_dm.dout_i_reg[12] ,
    p_1_in,
    SR,
    E,
    m_axi_rlast,
    CLK,
    dout,
    m_axi_rresp,
    \S_AXI_RRESP_ACC_reg[1]_0 ,
    D,
    \WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ,
    \WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ,
    m_axi_rdata,
    \WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 );
  output first_mi_word;
  output [0:0]Q;
  output \goreg_dm.dout_i_reg[9] ;
  output \length_counter_1_reg[4]_0 ;
  output [1:0]s_axi_rresp;
  output \current_word_1_reg[3]_0 ;
  output \current_word_1_reg[4]_0 ;
  output \current_word_1_reg[0]_0 ;
  output \current_word_1_reg[2]_0 ;
  output \current_word_1_reg[1]_0 ;
  output \goreg_dm.dout_i_reg[13] ;
  output \goreg_dm.dout_i_reg[12] ;
  output [255:0]p_1_in;
  input [0:0]SR;
  input [0:0]E;
  input m_axi_rlast;
  input CLK;
  input [20:0]dout;
  input [1:0]m_axi_rresp;
  input \S_AXI_RRESP_ACC_reg[1]_0 ;
  input [4:0]D;
  input [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ;
  input [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ;
  input [127:0]m_axi_rdata;
  input [0:0]\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [1:0]S_AXI_RRESP_ACC;
  wire \S_AXI_RRESP_ACC_reg[1]_0 ;
  wire [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ;
  wire [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ;
  wire [0:0]\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ;
  wire [4:0]current_word_1;
  wire \current_word_1_reg[0]_0 ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2]_0 ;
  wire \current_word_1_reg[3]_0 ;
  wire \current_word_1_reg[4]_0 ;
  wire [20:0]dout;
  wire first_mi_word;
  wire \goreg_dm.dout_i_reg[12] ;
  wire \goreg_dm.dout_i_reg[13] ;
  wire \goreg_dm.dout_i_reg[9] ;
  wire \length_counter_1[1]_i_1__0_n_0 ;
  wire \length_counter_1[2]_i_2__0_n_0 ;
  wire \length_counter_1[3]_i_2__0_n_0 ;
  wire \length_counter_1[4]_i_2__0_n_0 ;
  wire \length_counter_1[5]_i_2_n_0 ;
  wire \length_counter_1[6]_i_2__0_n_0 ;
  wire \length_counter_1[7]_i_2_n_0 ;
  wire [6:0]length_counter_1_reg;
  wire \length_counter_1_reg[4]_0 ;
  wire [127:0]m_axi_rdata;
  wire m_axi_rlast;
  wire [1:0]m_axi_rresp;
  wire [7:0]next_length_counter__0;
  wire [255:0]p_1_in;
  wire [1:0]s_axi_rresp;
  wire \s_axi_rresp[1]_INST_0_i_1_n_0 ;
  wire \s_axi_rresp[1]_INST_0_i_2_n_0 ;
  wire \s_axi_rresp[1]_INST_0_i_3_n_0 ;
  wire s_axi_rvalid_INST_0_i_8_n_0;
  wire s_axi_rvalid_INST_0_i_9_n_0;

  FDRE \S_AXI_RRESP_ACC_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(s_axi_rresp[0]),
        .Q(S_AXI_RRESP_ACC[0]),
        .R(SR));
  FDRE \S_AXI_RRESP_ACC_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(s_axi_rresp[1]),
        .Q(S_AXI_RRESP_ACC[1]),
        .R(SR));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[0] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[0]),
        .Q(p_1_in[0]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[100] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[100]),
        .Q(p_1_in[100]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[101] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[101]),
        .Q(p_1_in[101]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[102] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[102]),
        .Q(p_1_in[102]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[103] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[103]),
        .Q(p_1_in[103]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[104] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[104]),
        .Q(p_1_in[104]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[105] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[105]),
        .Q(p_1_in[105]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[106] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[106]),
        .Q(p_1_in[106]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[107] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[107]),
        .Q(p_1_in[107]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[108] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[108]),
        .Q(p_1_in[108]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[109] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[109]),
        .Q(p_1_in[109]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[10] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[10]),
        .Q(p_1_in[10]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[110] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[110]),
        .Q(p_1_in[110]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[111] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[111]),
        .Q(p_1_in[111]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[112] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[112]),
        .Q(p_1_in[112]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[113] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[113]),
        .Q(p_1_in[113]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[114] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[114]),
        .Q(p_1_in[114]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[115] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[115]),
        .Q(p_1_in[115]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[116] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[116]),
        .Q(p_1_in[116]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[117] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[117]),
        .Q(p_1_in[117]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[118] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[118]),
        .Q(p_1_in[118]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[119] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[119]),
        .Q(p_1_in[119]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[11] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[11]),
        .Q(p_1_in[11]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[120] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[120]),
        .Q(p_1_in[120]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[121] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[121]),
        .Q(p_1_in[121]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[122] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[122]),
        .Q(p_1_in[122]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[123] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[123]),
        .Q(p_1_in[123]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[124] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[124]),
        .Q(p_1_in[124]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[125] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[125]),
        .Q(p_1_in[125]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[126] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[126]),
        .Q(p_1_in[126]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[127] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[127]),
        .Q(p_1_in[127]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[12] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[12]),
        .Q(p_1_in[12]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[13] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[13]),
        .Q(p_1_in[13]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[14] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[14]),
        .Q(p_1_in[14]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[15] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[15]),
        .Q(p_1_in[15]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[16] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[16]),
        .Q(p_1_in[16]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[17] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[17]),
        .Q(p_1_in[17]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[18] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[18]),
        .Q(p_1_in[18]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[19] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[19]),
        .Q(p_1_in[19]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[1] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[1]),
        .Q(p_1_in[1]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[20] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[20]),
        .Q(p_1_in[20]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[21] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[21]),
        .Q(p_1_in[21]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[22] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[22]),
        .Q(p_1_in[22]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[23] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[23]),
        .Q(p_1_in[23]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[24] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[24]),
        .Q(p_1_in[24]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[25] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[25]),
        .Q(p_1_in[25]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[26] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[26]),
        .Q(p_1_in[26]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[27] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[27]),
        .Q(p_1_in[27]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[28] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[28]),
        .Q(p_1_in[28]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[29] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[29]),
        .Q(p_1_in[29]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[2] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[2]),
        .Q(p_1_in[2]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[30] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[30]),
        .Q(p_1_in[30]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[31] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[31]),
        .Q(p_1_in[31]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[32] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[32]),
        .Q(p_1_in[32]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[33] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[33]),
        .Q(p_1_in[33]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[34] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[34]),
        .Q(p_1_in[34]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[35] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[35]),
        .Q(p_1_in[35]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[36] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[36]),
        .Q(p_1_in[36]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[37] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[37]),
        .Q(p_1_in[37]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[38] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[38]),
        .Q(p_1_in[38]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[39] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[39]),
        .Q(p_1_in[39]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[3] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[3]),
        .Q(p_1_in[3]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[40] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[40]),
        .Q(p_1_in[40]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[41] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[41]),
        .Q(p_1_in[41]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[42] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[42]),
        .Q(p_1_in[42]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[43] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[43]),
        .Q(p_1_in[43]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[44] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[44]),
        .Q(p_1_in[44]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[45] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[45]),
        .Q(p_1_in[45]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[46] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[46]),
        .Q(p_1_in[46]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[47] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[47]),
        .Q(p_1_in[47]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[48] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[48]),
        .Q(p_1_in[48]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[49] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[49]),
        .Q(p_1_in[49]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[4] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[4]),
        .Q(p_1_in[4]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[50] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[50]),
        .Q(p_1_in[50]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[51] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[51]),
        .Q(p_1_in[51]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[52] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[52]),
        .Q(p_1_in[52]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[53] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[53]),
        .Q(p_1_in[53]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[54] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[54]),
        .Q(p_1_in[54]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[55] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[55]),
        .Q(p_1_in[55]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[56] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[56]),
        .Q(p_1_in[56]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[57] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[57]),
        .Q(p_1_in[57]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[58] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[58]),
        .Q(p_1_in[58]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[59] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[59]),
        .Q(p_1_in[59]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[5] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[5]),
        .Q(p_1_in[5]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[60] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[60]),
        .Q(p_1_in[60]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[61] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[61]),
        .Q(p_1_in[61]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[62] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[62]),
        .Q(p_1_in[62]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[63] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[63]),
        .Q(p_1_in[63]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[64] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[64]),
        .Q(p_1_in[64]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[65] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[65]),
        .Q(p_1_in[65]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[66] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[66]),
        .Q(p_1_in[66]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[67] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[67]),
        .Q(p_1_in[67]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[68] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[68]),
        .Q(p_1_in[68]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[69] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[69]),
        .Q(p_1_in[69]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[6] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[6]),
        .Q(p_1_in[6]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[70] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[70]),
        .Q(p_1_in[70]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[71] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[71]),
        .Q(p_1_in[71]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[72] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[72]),
        .Q(p_1_in[72]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[73] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[73]),
        .Q(p_1_in[73]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[74] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[74]),
        .Q(p_1_in[74]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[75] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[75]),
        .Q(p_1_in[75]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[76] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[76]),
        .Q(p_1_in[76]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[77] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[77]),
        .Q(p_1_in[77]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[78] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[78]),
        .Q(p_1_in[78]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[79] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[79]),
        .Q(p_1_in[79]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[7] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[7]),
        .Q(p_1_in[7]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[80] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[80]),
        .Q(p_1_in[80]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[81] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[81]),
        .Q(p_1_in[81]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[82] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[82]),
        .Q(p_1_in[82]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[83] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[83]),
        .Q(p_1_in[83]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[84] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[84]),
        .Q(p_1_in[84]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[85] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[85]),
        .Q(p_1_in[85]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[86] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[86]),
        .Q(p_1_in[86]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[87] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[87]),
        .Q(p_1_in[87]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[88] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[88]),
        .Q(p_1_in[88]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[89] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[89]),
        .Q(p_1_in[89]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[8] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[8]),
        .Q(p_1_in[8]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[90] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[90]),
        .Q(p_1_in[90]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[91] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[91]),
        .Q(p_1_in[91]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[92] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[92]),
        .Q(p_1_in[92]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[93] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[93]),
        .Q(p_1_in[93]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[94] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[94]),
        .Q(p_1_in[94]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[95] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[95]),
        .Q(p_1_in[95]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[96] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[96]),
        .Q(p_1_in[96]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[97] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[97]),
        .Q(p_1_in[97]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[98] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[98]),
        .Q(p_1_in[98]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[99] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[99]),
        .Q(p_1_in[99]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[9] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_1 ),
        .D(m_axi_rdata[9]),
        .Q(p_1_in[9]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[128] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[0]),
        .Q(p_1_in[128]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[129] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[1]),
        .Q(p_1_in[129]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[130] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[2]),
        .Q(p_1_in[130]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[131] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[3]),
        .Q(p_1_in[131]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[132] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[4]),
        .Q(p_1_in[132]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[133] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[5]),
        .Q(p_1_in[133]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[134] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[6]),
        .Q(p_1_in[134]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[135] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[7]),
        .Q(p_1_in[135]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[136] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[8]),
        .Q(p_1_in[136]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[137] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[9]),
        .Q(p_1_in[137]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[138] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[10]),
        .Q(p_1_in[138]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[139] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[11]),
        .Q(p_1_in[139]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[140] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[12]),
        .Q(p_1_in[140]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[141] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[13]),
        .Q(p_1_in[141]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[142] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[14]),
        .Q(p_1_in[142]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[143] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[15]),
        .Q(p_1_in[143]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[144] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[16]),
        .Q(p_1_in[144]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[145] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[17]),
        .Q(p_1_in[145]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[146] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[18]),
        .Q(p_1_in[146]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[147] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[19]),
        .Q(p_1_in[147]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[148] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[20]),
        .Q(p_1_in[148]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[149] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[21]),
        .Q(p_1_in[149]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[150] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[22]),
        .Q(p_1_in[150]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[151] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[23]),
        .Q(p_1_in[151]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[152] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[24]),
        .Q(p_1_in[152]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[153] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[25]),
        .Q(p_1_in[153]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[154] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[26]),
        .Q(p_1_in[154]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[155] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[27]),
        .Q(p_1_in[155]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[156] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[28]),
        .Q(p_1_in[156]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[157] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[29]),
        .Q(p_1_in[157]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[158] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[30]),
        .Q(p_1_in[158]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[159] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[31]),
        .Q(p_1_in[159]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[160] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[32]),
        .Q(p_1_in[160]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[161] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[33]),
        .Q(p_1_in[161]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[162] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[34]),
        .Q(p_1_in[162]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[163] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[35]),
        .Q(p_1_in[163]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[164] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[36]),
        .Q(p_1_in[164]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[165] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[37]),
        .Q(p_1_in[165]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[166] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[38]),
        .Q(p_1_in[166]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[167] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[39]),
        .Q(p_1_in[167]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[168] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[40]),
        .Q(p_1_in[168]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[169] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[41]),
        .Q(p_1_in[169]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[170] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[42]),
        .Q(p_1_in[170]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[171] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[43]),
        .Q(p_1_in[171]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[172] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[44]),
        .Q(p_1_in[172]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[173] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[45]),
        .Q(p_1_in[173]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[174] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[46]),
        .Q(p_1_in[174]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[175] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[47]),
        .Q(p_1_in[175]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[176] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[48]),
        .Q(p_1_in[176]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[177] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[49]),
        .Q(p_1_in[177]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[178] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[50]),
        .Q(p_1_in[178]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[179] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[51]),
        .Q(p_1_in[179]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[180] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[52]),
        .Q(p_1_in[180]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[181] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[53]),
        .Q(p_1_in[181]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[182] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[54]),
        .Q(p_1_in[182]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[183] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[55]),
        .Q(p_1_in[183]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[184] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[56]),
        .Q(p_1_in[184]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[185] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[57]),
        .Q(p_1_in[185]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[186] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[58]),
        .Q(p_1_in[186]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[187] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[59]),
        .Q(p_1_in[187]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[188] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[60]),
        .Q(p_1_in[188]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[189] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[61]),
        .Q(p_1_in[189]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[190] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[62]),
        .Q(p_1_in[190]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[191] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[63]),
        .Q(p_1_in[191]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[192] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[64]),
        .Q(p_1_in[192]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[193] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[65]),
        .Q(p_1_in[193]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[194] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[66]),
        .Q(p_1_in[194]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[195] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[67]),
        .Q(p_1_in[195]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[196] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[68]),
        .Q(p_1_in[196]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[197] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[69]),
        .Q(p_1_in[197]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[198] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[70]),
        .Q(p_1_in[198]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[199] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[71]),
        .Q(p_1_in[199]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[200] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[72]),
        .Q(p_1_in[200]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[201] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[73]),
        .Q(p_1_in[201]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[202] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[74]),
        .Q(p_1_in[202]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[203] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[75]),
        .Q(p_1_in[203]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[204] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[76]),
        .Q(p_1_in[204]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[205] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[77]),
        .Q(p_1_in[205]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[206] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[78]),
        .Q(p_1_in[206]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[207] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[79]),
        .Q(p_1_in[207]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[208] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[80]),
        .Q(p_1_in[208]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[209] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[81]),
        .Q(p_1_in[209]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[210] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[82]),
        .Q(p_1_in[210]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[211] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[83]),
        .Q(p_1_in[211]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[212] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[84]),
        .Q(p_1_in[212]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[213] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[85]),
        .Q(p_1_in[213]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[214] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[86]),
        .Q(p_1_in[214]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[215] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[87]),
        .Q(p_1_in[215]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[216] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[88]),
        .Q(p_1_in[216]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[217] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[89]),
        .Q(p_1_in[217]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[218] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[90]),
        .Q(p_1_in[218]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[219] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[91]),
        .Q(p_1_in[219]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[220] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[92]),
        .Q(p_1_in[220]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[221] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[93]),
        .Q(p_1_in[221]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[222] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[94]),
        .Q(p_1_in[222]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[223] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[95]),
        .Q(p_1_in[223]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[224] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[96]),
        .Q(p_1_in[224]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[225] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[97]),
        .Q(p_1_in[225]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[226] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[98]),
        .Q(p_1_in[226]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[227] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[99]),
        .Q(p_1_in[227]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[228] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[100]),
        .Q(p_1_in[228]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[229] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[101]),
        .Q(p_1_in[229]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[230] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[102]),
        .Q(p_1_in[230]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[231] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[103]),
        .Q(p_1_in[231]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[232] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[104]),
        .Q(p_1_in[232]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[233] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[105]),
        .Q(p_1_in[233]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[234] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[106]),
        .Q(p_1_in[234]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[235] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[107]),
        .Q(p_1_in[235]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[236] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[108]),
        .Q(p_1_in[236]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[237] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[109]),
        .Q(p_1_in[237]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[238] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[110]),
        .Q(p_1_in[238]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[239] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[111]),
        .Q(p_1_in[239]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[240] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[112]),
        .Q(p_1_in[240]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[241] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[113]),
        .Q(p_1_in[241]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[242] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[114]),
        .Q(p_1_in[242]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[243] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[115]),
        .Q(p_1_in[243]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[244] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[116]),
        .Q(p_1_in[244]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[245] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[117]),
        .Q(p_1_in[245]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[246] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[118]),
        .Q(p_1_in[246]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[247] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[119]),
        .Q(p_1_in[247]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[248] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[120]),
        .Q(p_1_in[248]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[249] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[121]),
        .Q(p_1_in[249]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[250] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[122]),
        .Q(p_1_in[250]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[251] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[123]),
        .Q(p_1_in[251]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[252] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[124]),
        .Q(p_1_in[252]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[253] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[125]),
        .Q(p_1_in[253]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[254] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[126]),
        .Q(p_1_in[254]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[255] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[255]_0 ),
        .D(m_axi_rdata[127]),
        .Q(p_1_in[255]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[127]_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \current_word_1[1]_i_2 
       (.I0(current_word_1[1]),
        .I1(first_mi_word),
        .I2(dout[20]),
        .I3(dout[15]),
        .O(\current_word_1_reg[1]_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \current_word_1[1]_i_3 
       (.I0(current_word_1[0]),
        .I1(first_mi_word),
        .I2(dout[20]),
        .I3(dout[14]),
        .O(\current_word_1_reg[0]_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \current_word_1[2]_i_2 
       (.I0(current_word_1[2]),
        .I1(first_mi_word),
        .I2(dout[20]),
        .I3(dout[16]),
        .O(\current_word_1_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h002E002C00000000)) 
    \current_word_1[3]_i_2 
       (.I0(\current_word_1_reg[1]_0 ),
        .I1(dout[12]),
        .I2(dout[11]),
        .I3(dout[13]),
        .I4(\current_word_1_reg[0]_0 ),
        .I5(\current_word_1_reg[2]_0 ),
        .O(\goreg_dm.dout_i_reg[12] ));
  FDRE \current_word_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(D[0]),
        .Q(current_word_1[0]),
        .R(SR));
  FDRE \current_word_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(D[1]),
        .Q(current_word_1[1]),
        .R(SR));
  FDRE \current_word_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(D[2]),
        .Q(current_word_1[2]),
        .R(SR));
  FDRE \current_word_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(D[3]),
        .Q(current_word_1[3]),
        .R(SR));
  FDRE \current_word_1_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(D[4]),
        .Q(current_word_1[4]),
        .R(SR));
  FDSE first_word_reg
       (.C(CLK),
        .CE(E),
        .D(m_axi_rlast),
        .Q(first_mi_word),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'h1D)) 
    \length_counter_1[0]_i_1__0 
       (.I0(length_counter_1_reg[0]),
        .I1(first_mi_word),
        .I2(dout[3]),
        .O(next_length_counter__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT5 #(
    .INIT(32'hCCA533A5)) 
    \length_counter_1[1]_i_1__0 
       (.I0(length_counter_1_reg[1]),
        .I1(dout[4]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(dout[3]),
        .O(\length_counter_1[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEFA051111FA05)) 
    \length_counter_1[2]_i_1__0 
       (.I0(\length_counter_1[2]_i_2__0_n_0 ),
        .I1(dout[4]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(dout[5]),
        .O(next_length_counter__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \length_counter_1[2]_i_2__0 
       (.I0(dout[3]),
        .I1(first_mi_word),
        .I2(length_counter_1_reg[0]),
        .O(\length_counter_1[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[3]_i_1__0 
       (.I0(length_counter_1_reg[3]),
        .I1(dout[6]),
        .I2(dout[5]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[2]),
        .I5(\length_counter_1[3]_i_2__0_n_0 ),
        .O(next_length_counter__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT5 #(
    .INIT(32'h00053305)) 
    \length_counter_1[3]_i_2__0 
       (.I0(length_counter_1_reg[1]),
        .I1(dout[4]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(dout[3]),
        .O(\length_counter_1[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[4]_i_1__0 
       (.I0(dout[6]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2__0_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(dout[7]),
        .O(next_length_counter__0[4]));
  LUT6 #(
    .INIT(64'h0000000511110005)) 
    \length_counter_1[4]_i_2__0 
       (.I0(\length_counter_1[2]_i_2__0_n_0 ),
        .I1(dout[4]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(dout[5]),
        .O(\length_counter_1[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[5]_i_1__0 
       (.I0(length_counter_1_reg[5]),
        .I1(dout[8]),
        .I2(dout[7]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[4]),
        .I5(\length_counter_1[5]_i_2_n_0 ),
        .O(next_length_counter__0[5]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \length_counter_1[5]_i_2 
       (.I0(dout[5]),
        .I1(length_counter_1_reg[2]),
        .I2(\length_counter_1[3]_i_2__0_n_0 ),
        .I3(length_counter_1_reg[3]),
        .I4(first_mi_word),
        .I5(dout[6]),
        .O(\length_counter_1[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[6]_i_1__0 
       (.I0(length_counter_1_reg[6]),
        .I1(dout[9]),
        .I2(dout[8]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[5]),
        .I5(\length_counter_1[6]_i_2__0_n_0 ),
        .O(next_length_counter__0[6]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \length_counter_1[6]_i_2__0 
       (.I0(dout[6]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2__0_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(dout[7]),
        .O(\length_counter_1[6]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[7]_i_1__0 
       (.I0(Q),
        .I1(dout[10]),
        .I2(dout[9]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[6]),
        .I5(\length_counter_1[7]_i_2_n_0 ),
        .O(next_length_counter__0[7]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \length_counter_1[7]_i_2 
       (.I0(dout[7]),
        .I1(length_counter_1_reg[4]),
        .I2(\length_counter_1[5]_i_2_n_0 ),
        .I3(length_counter_1_reg[5]),
        .I4(first_mi_word),
        .I5(dout[8]),
        .O(\length_counter_1[7]_i_2_n_0 ));
  FDRE \length_counter_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[0]),
        .Q(length_counter_1_reg[0]),
        .R(SR));
  FDRE \length_counter_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\length_counter_1[1]_i_1__0_n_0 ),
        .Q(length_counter_1_reg[1]),
        .R(SR));
  FDRE \length_counter_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[2]),
        .Q(length_counter_1_reg[2]),
        .R(SR));
  FDRE \length_counter_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[3]),
        .Q(length_counter_1_reg[3]),
        .R(SR));
  FDRE \length_counter_1_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[4]),
        .Q(length_counter_1_reg[4]),
        .R(SR));
  FDRE \length_counter_1_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[5]),
        .Q(length_counter_1_reg[5]),
        .R(SR));
  FDRE \length_counter_1_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[6]),
        .Q(length_counter_1_reg[6]),
        .R(SR));
  FDRE \length_counter_1_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[7]),
        .Q(Q),
        .R(SR));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    m_axi_rready_INST_0_i_2
       (.I0(dout[9]),
        .I1(length_counter_1_reg[6]),
        .I2(\length_counter_1[7]_i_2_n_0 ),
        .I3(Q),
        .I4(first_mi_word),
        .I5(dout[10]),
        .O(\goreg_dm.dout_i_reg[9] ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \s_axi_rdata[255]_INST_0_i_2 
       (.I0(current_word_1[3]),
        .I1(first_mi_word),
        .I2(dout[20]),
        .I3(dout[17]),
        .O(\current_word_1_reg[3]_0 ));
  LUT4 #(
    .INIT(16'h01FD)) 
    \s_axi_rdata[255]_INST_0_i_4 
       (.I0(current_word_1[4]),
        .I1(first_mi_word),
        .I2(dout[20]),
        .I3(dout[18]),
        .O(\current_word_1_reg[4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \s_axi_rresp[0]_INST_0 
       (.I0(S_AXI_RRESP_ACC[0]),
        .I1(\s_axi_rresp[1]_INST_0_i_1_n_0 ),
        .I2(m_axi_rresp[0]),
        .O(s_axi_rresp[0]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \s_axi_rresp[1]_INST_0 
       (.I0(S_AXI_RRESP_ACC[1]),
        .I1(\s_axi_rresp[1]_INST_0_i_1_n_0 ),
        .I2(m_axi_rresp[1]),
        .O(s_axi_rresp[1]));
  LUT6 #(
    .INIT(64'h00000000EAEAEAFF)) 
    \s_axi_rresp[1]_INST_0_i_1 
       (.I0(\s_axi_rresp[1]_INST_0_i_2_n_0 ),
        .I1(\current_word_1_reg[3]_0 ),
        .I2(dout[2]),
        .I3(\S_AXI_RRESP_ACC_reg[1]_0 ),
        .I4(\current_word_1_reg[4]_0 ),
        .I5(\s_axi_rresp[1]_INST_0_i_3_n_0 ),
        .O(\s_axi_rresp[1]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFA0EEEAEEA0)) 
    \s_axi_rresp[1]_INST_0_i_2 
       (.I0(\current_word_1_reg[0]_0 ),
        .I1(\current_word_1_reg[2]_0 ),
        .I2(dout[0]),
        .I3(dout[2]),
        .I4(dout[1]),
        .I5(\current_word_1_reg[1]_0 ),
        .O(\s_axi_rresp[1]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7504)) 
    \s_axi_rresp[1]_INST_0_i_3 
       (.I0(S_AXI_RRESP_ACC[1]),
        .I1(S_AXI_RRESP_ACC[0]),
        .I2(m_axi_rresp[0]),
        .I3(m_axi_rresp[1]),
        .I4(dout[19]),
        .I5(first_mi_word),
        .O(\s_axi_rresp[1]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000044404)) 
    s_axi_rvalid_INST_0_i_5
       (.I0(s_axi_rvalid_INST_0_i_8_n_0),
        .I1(\length_counter_1[5]_i_2_n_0 ),
        .I2(length_counter_1_reg[4]),
        .I3(first_mi_word),
        .I4(dout[7]),
        .I5(s_axi_rvalid_INST_0_i_9_n_0),
        .O(\length_counter_1_reg[4]_0 ));
  LUT6 #(
    .INIT(64'h785A787878788778)) 
    s_axi_rvalid_INST_0_i_6
       (.I0(\current_word_1_reg[3]_0 ),
        .I1(\goreg_dm.dout_i_reg[12] ),
        .I2(\current_word_1_reg[4]_0 ),
        .I3(dout[13]),
        .I4(dout[12]),
        .I5(dout[11]),
        .O(\goreg_dm.dout_i_reg[13] ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    s_axi_rvalid_INST_0_i_8
       (.I0(dout[8]),
        .I1(first_mi_word),
        .I2(length_counter_1_reg[5]),
        .O(s_axi_rvalid_INST_0_i_8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    s_axi_rvalid_INST_0_i_9
       (.I0(dout[9]),
        .I1(first_mi_word),
        .I2(length_counter_1_reg[6]),
        .O(s_axi_rvalid_INST_0_i_9_n_0));
endmodule

(* C_AXI_ADDR_WIDTH = "64" *) (* C_AXI_IS_ACLK_ASYNC = "0" *) (* C_AXI_PROTOCOL = "0" *) 
(* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_WRITE = "1" *) (* C_FAMILY = "kintexu" *) 
(* C_FIFO_MODE = "0" *) (* C_MAX_SPLIT_BEATS = "256" *) (* C_M_AXI_ACLK_RATIO = "2" *) 
(* C_M_AXI_BYTES_LOG = "4" *) (* C_M_AXI_DATA_WIDTH = "128" *) (* C_PACKING_LEVEL = "1" *) 
(* C_RATIO = "2" *) (* C_RATIO_LOG = "1" *) (* C_SUPPORTS_ID = "1" *) 
(* C_SYNCHRONIZER_STAGE = "3" *) (* C_S_AXI_ACLK_RATIO = "1" *) (* C_S_AXI_BYTES_LOG = "5" *) 
(* C_S_AXI_DATA_WIDTH = "256" *) (* C_S_AXI_ID_WIDTH = "4" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_27_top" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *) 
(* P_AXILITE = "2" *) (* P_CONVERSION = "2" *) (* P_MAX_SPLIT_BEATS = "256" *) 
module axi4_dwtrans_axi_dwidth_converter_v2_1_27_top
   (s_axi_aclk,
    s_axi_aresetn,
    s_axi_awid,
    s_axi_awaddr,
    s_axi_awlen,
    s_axi_awsize,
    s_axi_awburst,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos,
    s_axi_awvalid,
    s_axi_awready,
    s_axi_wdata,
    s_axi_wstrb,
    s_axi_wlast,
    s_axi_wvalid,
    s_axi_wready,
    s_axi_bid,
    s_axi_bresp,
    s_axi_bvalid,
    s_axi_bready,
    s_axi_arid,
    s_axi_araddr,
    s_axi_arlen,
    s_axi_arsize,
    s_axi_arburst,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos,
    s_axi_arvalid,
    s_axi_arready,
    s_axi_rid,
    s_axi_rdata,
    s_axi_rresp,
    s_axi_rlast,
    s_axi_rvalid,
    s_axi_rready,
    m_axi_aclk,
    m_axi_aresetn,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    m_axi_awvalid,
    m_axi_awready,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wvalid,
    m_axi_wready,
    m_axi_bresp,
    m_axi_bvalid,
    m_axi_bready,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    m_axi_arvalid,
    m_axi_arready,
    m_axi_rdata,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_rvalid,
    m_axi_rready);
  (* keep = "true" *) input s_axi_aclk;
  (* keep = "true" *) input s_axi_aresetn;
  input [3:0]s_axi_awid;
  input [63:0]s_axi_awaddr;
  input [7:0]s_axi_awlen;
  input [2:0]s_axi_awsize;
  input [1:0]s_axi_awburst;
  input [0:0]s_axi_awlock;
  input [3:0]s_axi_awcache;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awregion;
  input [3:0]s_axi_awqos;
  input s_axi_awvalid;
  output s_axi_awready;
  input [255:0]s_axi_wdata;
  input [31:0]s_axi_wstrb;
  input s_axi_wlast;
  input s_axi_wvalid;
  output s_axi_wready;
  output [3:0]s_axi_bid;
  output [1:0]s_axi_bresp;
  output s_axi_bvalid;
  input s_axi_bready;
  input [3:0]s_axi_arid;
  input [63:0]s_axi_araddr;
  input [7:0]s_axi_arlen;
  input [2:0]s_axi_arsize;
  input [1:0]s_axi_arburst;
  input [0:0]s_axi_arlock;
  input [3:0]s_axi_arcache;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arregion;
  input [3:0]s_axi_arqos;
  input s_axi_arvalid;
  output s_axi_arready;
  output [3:0]s_axi_rid;
  output [255:0]s_axi_rdata;
  output [1:0]s_axi_rresp;
  output s_axi_rlast;
  output s_axi_rvalid;
  input s_axi_rready;
  (* keep = "true" *) input m_axi_aclk;
  (* keep = "true" *) input m_axi_aresetn;
  output [63:0]m_axi_awaddr;
  output [7:0]m_axi_awlen;
  output [2:0]m_axi_awsize;
  output [1:0]m_axi_awburst;
  output [0:0]m_axi_awlock;
  output [3:0]m_axi_awcache;
  output [2:0]m_axi_awprot;
  output [3:0]m_axi_awregion;
  output [3:0]m_axi_awqos;
  output m_axi_awvalid;
  input m_axi_awready;
  output [127:0]m_axi_wdata;
  output [15:0]m_axi_wstrb;
  output m_axi_wlast;
  output m_axi_wvalid;
  input m_axi_wready;
  input [1:0]m_axi_bresp;
  input m_axi_bvalid;
  output m_axi_bready;
  output [63:0]m_axi_araddr;
  output [7:0]m_axi_arlen;
  output [2:0]m_axi_arsize;
  output [1:0]m_axi_arburst;
  output [0:0]m_axi_arlock;
  output [3:0]m_axi_arcache;
  output [2:0]m_axi_arprot;
  output [3:0]m_axi_arregion;
  output [3:0]m_axi_arqos;
  output m_axi_arvalid;
  input m_axi_arready;
  input [127:0]m_axi_rdata;
  input [1:0]m_axi_rresp;
  input m_axi_rlast;
  input m_axi_rvalid;
  output m_axi_rready;

  (* RTL_KEEP = "true" *) wire m_axi_aclk;
  wire [63:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  (* RTL_KEEP = "true" *) wire m_axi_aresetn;
  wire [7:0]m_axi_arlen;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire [3:0]m_axi_arregion;
  wire [2:0]m_axi_arsize;
  wire m_axi_arvalid;
  wire [63:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [7:0]m_axi_awlen;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire [2:0]m_axi_awsize;
  wire m_axi_awvalid;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [127:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire [1:0]m_axi_rresp;
  wire m_axi_rvalid;
  wire [127:0]m_axi_wdata;
  wire m_axi_wlast;
  wire m_axi_wready;
  wire [15:0]m_axi_wstrb;
  wire m_axi_wvalid;
  (* RTL_KEEP = "true" *) wire s_axi_aclk;
  wire [63:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  (* RTL_KEEP = "true" *) wire s_axi_aresetn;
  wire [3:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire s_axi_arready;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [63:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [3:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire s_axi_awready;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [3:0]s_axi_bid;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire [255:0]s_axi_rdata;
  wire [3:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire s_axi_rvalid;
  wire [255:0]s_axi_wdata;
  wire s_axi_wready;
  wire [31:0]s_axi_wstrb;
  wire s_axi_wvalid;

  axi4_dwtrans_axi_dwidth_converter_v2_1_27_axi_downsizer \gen_downsizer.gen_simple_downsizer.axi_downsizer_inst 
       (.CLK(s_axi_aclk),
        .E(s_axi_awready),
        .S_AXI_AREADY_I_reg(s_axi_arready),
        .\S_AXI_ASIZE_Q_reg[2] ({m_axi_arsize,m_axi_arlen}),
        .command_ongoing_reg(m_axi_awvalid),
        .command_ongoing_reg_0(m_axi_arvalid),
        .din({m_axi_awsize,m_axi_awlen}),
        .\goreg_dm.dout_i_reg[9] (m_axi_wlast),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arqos(m_axi_arqos),
        .m_axi_arready(m_axi_arready),
        .m_axi_arregion(m_axi_arregion),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awqos(m_axi_awqos),
        .m_axi_awready(m_axi_awready),
        .m_axi_awregion(m_axi_awregion),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wvalid(m_axi_wvalid),
        .out(s_axi_aresetn),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arregion(s_axi_arregion),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awregion(s_axi_awregion),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bid(s_axi_bid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_bvalid(s_axi_bvalid),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rresp(s_axi_rresp),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wready(s_axi_wready),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wvalid(s_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_27_w_downsizer" *) 
module axi4_dwtrans_axi_dwidth_converter_v2_1_27_w_downsizer
   (first_mi_word,
    \goreg_dm.dout_i_reg[9] ,
    m_axi_wstrb,
    m_axi_wdata,
    \current_word_1_reg[3]_0 ,
    \current_word_1_reg[4]_0 ,
    Q,
    \current_word_1_reg[2]_0 ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[0]_0 ,
    SR,
    E,
    CLK,
    \current_word_1_reg[1]_1 ,
    s_axi_wstrb,
    s_axi_wdata,
    D);
  output first_mi_word;
  output \goreg_dm.dout_i_reg[9] ;
  output [15:0]m_axi_wstrb;
  output [127:0]m_axi_wdata;
  output \current_word_1_reg[3]_0 ;
  output \current_word_1_reg[4]_0 ;
  output [1:0]Q;
  output \current_word_1_reg[2]_0 ;
  output \current_word_1_reg[1]_0 ;
  output \current_word_1_reg[0]_0 ;
  input [0:0]SR;
  input [0:0]E;
  input CLK;
  input [18:0]\current_word_1_reg[1]_1 ;
  input [31:0]s_axi_wstrb;
  input [255:0]s_axi_wdata;
  input [4:0]D;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [4:0]current_word_1;
  wire \current_word_1_reg[0]_0 ;
  wire \current_word_1_reg[1]_0 ;
  wire [18:0]\current_word_1_reg[1]_1 ;
  wire \current_word_1_reg[2]_0 ;
  wire \current_word_1_reg[3]_0 ;
  wire \current_word_1_reg[4]_0 ;
  wire first_mi_word;
  wire \goreg_dm.dout_i_reg[9] ;
  wire \length_counter_1[1]_i_1_n_0 ;
  wire \length_counter_1[2]_i_2_n_0 ;
  wire \length_counter_1[3]_i_2_n_0 ;
  wire \length_counter_1[4]_i_2_n_0 ;
  wire \length_counter_1[6]_i_2_n_0 ;
  wire [7:0]length_counter_1_reg;
  wire [127:0]m_axi_wdata;
  wire \m_axi_wdata[127]_INST_0_i_1_n_0 ;
  wire \m_axi_wdata[127]_INST_0_i_2_n_0 ;
  wire m_axi_wlast_INST_0_i_1_n_0;
  wire m_axi_wlast_INST_0_i_2_n_0;
  wire [15:0]m_axi_wstrb;
  wire [7:0]next_length_counter;
  wire [255:0]s_axi_wdata;
  wire [31:0]s_axi_wstrb;

  LUT4 #(
    .INIT(16'hFE02)) 
    \current_word_1[1]_i_2__0 
       (.I0(current_word_1[1]),
        .I1(\current_word_1_reg[1]_1 [18]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [14]),
        .O(\current_word_1_reg[1]_0 ));
  LUT4 #(
    .INIT(16'h01FD)) 
    \current_word_1[1]_i_3__0 
       (.I0(current_word_1[0]),
        .I1(\current_word_1_reg[1]_1 [18]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [13]),
        .O(\current_word_1_reg[0]_0 ));
  FDRE \current_word_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(D[0]),
        .Q(current_word_1[0]),
        .R(SR));
  FDRE \current_word_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(D[1]),
        .Q(current_word_1[1]),
        .R(SR));
  FDRE \current_word_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(D[2]),
        .Q(Q[0]),
        .R(SR));
  FDRE \current_word_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(D[3]),
        .Q(Q[1]),
        .R(SR));
  FDRE \current_word_1_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(D[4]),
        .Q(current_word_1[4]),
        .R(SR));
  FDSE first_word_reg
       (.C(CLK),
        .CE(E),
        .D(\goreg_dm.dout_i_reg[9] ),
        .Q(first_mi_word),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'h1D)) 
    \length_counter_1[0]_i_1 
       (.I0(length_counter_1_reg[0]),
        .I1(first_mi_word),
        .I2(\current_word_1_reg[1]_1 [0]),
        .O(next_length_counter[0]));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'hCCA533A5)) 
    \length_counter_1[1]_i_1 
       (.I0(length_counter_1_reg[1]),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(\current_word_1_reg[1]_1 [0]),
        .O(\length_counter_1[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEFA051111FA05)) 
    \length_counter_1[2]_i_1 
       (.I0(\length_counter_1[2]_i_2_n_0 ),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [2]),
        .O(next_length_counter[2]));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \length_counter_1[2]_i_2 
       (.I0(\current_word_1_reg[1]_1 [0]),
        .I1(first_mi_word),
        .I2(length_counter_1_reg[0]),
        .O(\length_counter_1[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[3]_i_1 
       (.I0(length_counter_1_reg[3]),
        .I1(\current_word_1_reg[1]_1 [3]),
        .I2(\current_word_1_reg[1]_1 [2]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[2]),
        .I5(\length_counter_1[3]_i_2_n_0 ),
        .O(next_length_counter[3]));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'h00053305)) 
    \length_counter_1[3]_i_2 
       (.I0(length_counter_1_reg[1]),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(\current_word_1_reg[1]_1 [0]),
        .O(\length_counter_1[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[4]_i_1 
       (.I0(\current_word_1_reg[1]_1 [3]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [4]),
        .O(next_length_counter[4]));
  LUT6 #(
    .INIT(64'h0000000511110005)) 
    \length_counter_1[4]_i_2 
       (.I0(\length_counter_1[2]_i_2_n_0 ),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [2]),
        .O(\length_counter_1[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[5]_i_1 
       (.I0(\current_word_1_reg[1]_1 [4]),
        .I1(length_counter_1_reg[4]),
        .I2(m_axi_wlast_INST_0_i_2_n_0),
        .I3(length_counter_1_reg[5]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [5]),
        .O(next_length_counter[5]));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[6]_i_1 
       (.I0(\current_word_1_reg[1]_1 [5]),
        .I1(length_counter_1_reg[5]),
        .I2(\length_counter_1[6]_i_2_n_0 ),
        .I3(length_counter_1_reg[6]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [6]),
        .O(next_length_counter[6]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \length_counter_1[6]_i_2 
       (.I0(\current_word_1_reg[1]_1 [3]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [4]),
        .O(\length_counter_1[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[7]_i_1 
       (.I0(\current_word_1_reg[1]_1 [6]),
        .I1(length_counter_1_reg[6]),
        .I2(m_axi_wlast_INST_0_i_1_n_0),
        .I3(length_counter_1_reg[7]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [7]),
        .O(next_length_counter[7]));
  FDRE \length_counter_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[0]),
        .Q(length_counter_1_reg[0]),
        .R(SR));
  FDRE \length_counter_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\length_counter_1[1]_i_1_n_0 ),
        .Q(length_counter_1_reg[1]),
        .R(SR));
  FDRE \length_counter_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[2]),
        .Q(length_counter_1_reg[2]),
        .R(SR));
  FDRE \length_counter_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[3]),
        .Q(length_counter_1_reg[3]),
        .R(SR));
  FDRE \length_counter_1_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[4]),
        .Q(length_counter_1_reg[4]),
        .R(SR));
  FDRE \length_counter_1_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[5]),
        .Q(length_counter_1_reg[5]),
        .R(SR));
  FDRE \length_counter_1_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[6]),
        .Q(length_counter_1_reg[6]),
        .R(SR));
  FDRE \length_counter_1_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[7]),
        .Q(length_counter_1_reg[7]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[0]_INST_0 
       (.I0(s_axi_wdata[0]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[128]),
        .O(m_axi_wdata[0]));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[100]_INST_0 
       (.I0(s_axi_wdata[100]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[228]),
        .O(m_axi_wdata[100]));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[101]_INST_0 
       (.I0(s_axi_wdata[101]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[229]),
        .O(m_axi_wdata[101]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[102]_INST_0 
       (.I0(s_axi_wdata[102]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[230]),
        .O(m_axi_wdata[102]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[103]_INST_0 
       (.I0(s_axi_wdata[103]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[231]),
        .O(m_axi_wdata[103]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[104]_INST_0 
       (.I0(s_axi_wdata[104]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[232]),
        .O(m_axi_wdata[104]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[105]_INST_0 
       (.I0(s_axi_wdata[105]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[233]),
        .O(m_axi_wdata[105]));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[106]_INST_0 
       (.I0(s_axi_wdata[106]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[234]),
        .O(m_axi_wdata[106]));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[107]_INST_0 
       (.I0(s_axi_wdata[107]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[235]),
        .O(m_axi_wdata[107]));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[108]_INST_0 
       (.I0(s_axi_wdata[108]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[236]),
        .O(m_axi_wdata[108]));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[109]_INST_0 
       (.I0(s_axi_wdata[109]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[237]),
        .O(m_axi_wdata[109]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[10]_INST_0 
       (.I0(s_axi_wdata[10]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[138]),
        .O(m_axi_wdata[10]));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[110]_INST_0 
       (.I0(s_axi_wdata[110]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[238]),
        .O(m_axi_wdata[110]));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[111]_INST_0 
       (.I0(s_axi_wdata[111]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[239]),
        .O(m_axi_wdata[111]));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[112]_INST_0 
       (.I0(s_axi_wdata[112]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[240]),
        .O(m_axi_wdata[112]));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[113]_INST_0 
       (.I0(s_axi_wdata[113]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[241]),
        .O(m_axi_wdata[113]));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[114]_INST_0 
       (.I0(s_axi_wdata[114]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[242]),
        .O(m_axi_wdata[114]));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[115]_INST_0 
       (.I0(s_axi_wdata[115]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[243]),
        .O(m_axi_wdata[115]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[116]_INST_0 
       (.I0(s_axi_wdata[116]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[244]),
        .O(m_axi_wdata[116]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[117]_INST_0 
       (.I0(s_axi_wdata[117]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[245]),
        .O(m_axi_wdata[117]));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[118]_INST_0 
       (.I0(s_axi_wdata[118]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[246]),
        .O(m_axi_wdata[118]));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[119]_INST_0 
       (.I0(s_axi_wdata[119]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[247]),
        .O(m_axi_wdata[119]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[11]_INST_0 
       (.I0(s_axi_wdata[11]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[139]),
        .O(m_axi_wdata[11]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[120]_INST_0 
       (.I0(s_axi_wdata[120]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[248]),
        .O(m_axi_wdata[120]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[121]_INST_0 
       (.I0(s_axi_wdata[121]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[249]),
        .O(m_axi_wdata[121]));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[122]_INST_0 
       (.I0(s_axi_wdata[122]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[250]),
        .O(m_axi_wdata[122]));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[123]_INST_0 
       (.I0(s_axi_wdata[123]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[251]),
        .O(m_axi_wdata[123]));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[124]_INST_0 
       (.I0(s_axi_wdata[124]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[252]),
        .O(m_axi_wdata[124]));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[125]_INST_0 
       (.I0(s_axi_wdata[125]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[253]),
        .O(m_axi_wdata[125]));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[126]_INST_0 
       (.I0(s_axi_wdata[126]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[254]),
        .O(m_axi_wdata[126]));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[127]_INST_0 
       (.I0(s_axi_wdata[127]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[255]),
        .O(m_axi_wdata[127]));
  LUT5 #(
    .INIT(32'h17E8E817)) 
    \m_axi_wdata[127]_INST_0_i_1 
       (.I0(\m_axi_wdata[127]_INST_0_i_2_n_0 ),
        .I1(\current_word_1_reg[3]_0 ),
        .I2(\current_word_1_reg[1]_1 [11]),
        .I3(\current_word_1_reg[4]_0 ),
        .I4(\current_word_1_reg[1]_1 [12]),
        .O(\m_axi_wdata[127]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hE888E888EEE8E888)) 
    \m_axi_wdata[127]_INST_0_i_2 
       (.I0(\current_word_1_reg[2]_0 ),
        .I1(\current_word_1_reg[1]_1 [10]),
        .I2(\current_word_1_reg[1]_0 ),
        .I3(\current_word_1_reg[1]_1 [9]),
        .I4(\current_word_1_reg[1]_1 [8]),
        .I5(\current_word_1_reg[0]_0 ),
        .O(\m_axi_wdata[127]_INST_0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \m_axi_wdata[127]_INST_0_i_3 
       (.I0(Q[1]),
        .I1(\current_word_1_reg[1]_1 [18]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [16]),
        .O(\current_word_1_reg[3]_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \m_axi_wdata[127]_INST_0_i_4 
       (.I0(current_word_1[4]),
        .I1(\current_word_1_reg[1]_1 [18]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [17]),
        .O(\current_word_1_reg[4]_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \m_axi_wdata[127]_INST_0_i_5 
       (.I0(Q[0]),
        .I1(\current_word_1_reg[1]_1 [18]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [15]),
        .O(\current_word_1_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[12]_INST_0 
       (.I0(s_axi_wdata[12]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[140]),
        .O(m_axi_wdata[12]));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[13]_INST_0 
       (.I0(s_axi_wdata[13]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[141]),
        .O(m_axi_wdata[13]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[14]_INST_0 
       (.I0(s_axi_wdata[14]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[142]),
        .O(m_axi_wdata[14]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[15]_INST_0 
       (.I0(s_axi_wdata[15]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[143]),
        .O(m_axi_wdata[15]));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[16]_INST_0 
       (.I0(s_axi_wdata[16]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[144]),
        .O(m_axi_wdata[16]));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[17]_INST_0 
       (.I0(s_axi_wdata[17]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[145]),
        .O(m_axi_wdata[17]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[18]_INST_0 
       (.I0(s_axi_wdata[18]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[146]),
        .O(m_axi_wdata[18]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[19]_INST_0 
       (.I0(s_axi_wdata[19]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[147]),
        .O(m_axi_wdata[19]));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[1]_INST_0 
       (.I0(s_axi_wdata[1]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[129]),
        .O(m_axi_wdata[1]));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[20]_INST_0 
       (.I0(s_axi_wdata[20]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[148]),
        .O(m_axi_wdata[20]));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[21]_INST_0 
       (.I0(s_axi_wdata[21]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[149]),
        .O(m_axi_wdata[21]));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[22]_INST_0 
       (.I0(s_axi_wdata[22]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[150]),
        .O(m_axi_wdata[22]));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[23]_INST_0 
       (.I0(s_axi_wdata[23]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[151]),
        .O(m_axi_wdata[23]));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[24]_INST_0 
       (.I0(s_axi_wdata[24]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[152]),
        .O(m_axi_wdata[24]));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[25]_INST_0 
       (.I0(s_axi_wdata[25]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[153]),
        .O(m_axi_wdata[25]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[26]_INST_0 
       (.I0(s_axi_wdata[26]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[154]),
        .O(m_axi_wdata[26]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[27]_INST_0 
       (.I0(s_axi_wdata[27]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[155]),
        .O(m_axi_wdata[27]));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[28]_INST_0 
       (.I0(s_axi_wdata[28]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[156]),
        .O(m_axi_wdata[28]));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[29]_INST_0 
       (.I0(s_axi_wdata[29]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[157]),
        .O(m_axi_wdata[29]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[2]_INST_0 
       (.I0(s_axi_wdata[2]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[130]),
        .O(m_axi_wdata[2]));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[30]_INST_0 
       (.I0(s_axi_wdata[30]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[158]),
        .O(m_axi_wdata[30]));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[31]_INST_0 
       (.I0(s_axi_wdata[31]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[159]),
        .O(m_axi_wdata[31]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[32]_INST_0 
       (.I0(s_axi_wdata[32]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[160]),
        .O(m_axi_wdata[32]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[33]_INST_0 
       (.I0(s_axi_wdata[33]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[161]),
        .O(m_axi_wdata[33]));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[34]_INST_0 
       (.I0(s_axi_wdata[34]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[162]),
        .O(m_axi_wdata[34]));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[35]_INST_0 
       (.I0(s_axi_wdata[35]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[163]),
        .O(m_axi_wdata[35]));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[36]_INST_0 
       (.I0(s_axi_wdata[36]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[164]),
        .O(m_axi_wdata[36]));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[37]_INST_0 
       (.I0(s_axi_wdata[37]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[165]),
        .O(m_axi_wdata[37]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[38]_INST_0 
       (.I0(s_axi_wdata[38]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[166]),
        .O(m_axi_wdata[38]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[39]_INST_0 
       (.I0(s_axi_wdata[39]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[167]),
        .O(m_axi_wdata[39]));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[3]_INST_0 
       (.I0(s_axi_wdata[3]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[131]),
        .O(m_axi_wdata[3]));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[40]_INST_0 
       (.I0(s_axi_wdata[40]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[168]),
        .O(m_axi_wdata[40]));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[41]_INST_0 
       (.I0(s_axi_wdata[41]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[169]),
        .O(m_axi_wdata[41]));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[42]_INST_0 
       (.I0(s_axi_wdata[42]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[170]),
        .O(m_axi_wdata[42]));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[43]_INST_0 
       (.I0(s_axi_wdata[43]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[171]),
        .O(m_axi_wdata[43]));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[44]_INST_0 
       (.I0(s_axi_wdata[44]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[172]),
        .O(m_axi_wdata[44]));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[45]_INST_0 
       (.I0(s_axi_wdata[45]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[173]),
        .O(m_axi_wdata[45]));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[46]_INST_0 
       (.I0(s_axi_wdata[46]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[174]),
        .O(m_axi_wdata[46]));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[47]_INST_0 
       (.I0(s_axi_wdata[47]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[175]),
        .O(m_axi_wdata[47]));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[48]_INST_0 
       (.I0(s_axi_wdata[48]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[176]),
        .O(m_axi_wdata[48]));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[49]_INST_0 
       (.I0(s_axi_wdata[49]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[177]),
        .O(m_axi_wdata[49]));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[4]_INST_0 
       (.I0(s_axi_wdata[4]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[132]),
        .O(m_axi_wdata[4]));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[50]_INST_0 
       (.I0(s_axi_wdata[50]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[178]),
        .O(m_axi_wdata[50]));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[51]_INST_0 
       (.I0(s_axi_wdata[51]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[179]),
        .O(m_axi_wdata[51]));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[52]_INST_0 
       (.I0(s_axi_wdata[52]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[180]),
        .O(m_axi_wdata[52]));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[53]_INST_0 
       (.I0(s_axi_wdata[53]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[181]),
        .O(m_axi_wdata[53]));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[54]_INST_0 
       (.I0(s_axi_wdata[54]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[182]),
        .O(m_axi_wdata[54]));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[55]_INST_0 
       (.I0(s_axi_wdata[55]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[183]),
        .O(m_axi_wdata[55]));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[56]_INST_0 
       (.I0(s_axi_wdata[56]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[184]),
        .O(m_axi_wdata[56]));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[57]_INST_0 
       (.I0(s_axi_wdata[57]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[185]),
        .O(m_axi_wdata[57]));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[58]_INST_0 
       (.I0(s_axi_wdata[58]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[186]),
        .O(m_axi_wdata[58]));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[59]_INST_0 
       (.I0(s_axi_wdata[59]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[187]),
        .O(m_axi_wdata[59]));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[5]_INST_0 
       (.I0(s_axi_wdata[5]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[133]),
        .O(m_axi_wdata[5]));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[60]_INST_0 
       (.I0(s_axi_wdata[60]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[188]),
        .O(m_axi_wdata[60]));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[61]_INST_0 
       (.I0(s_axi_wdata[61]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[189]),
        .O(m_axi_wdata[61]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[62]_INST_0 
       (.I0(s_axi_wdata[62]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[190]),
        .O(m_axi_wdata[62]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[63]_INST_0 
       (.I0(s_axi_wdata[63]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[191]),
        .O(m_axi_wdata[63]));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[64]_INST_0 
       (.I0(s_axi_wdata[64]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[192]),
        .O(m_axi_wdata[64]));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[65]_INST_0 
       (.I0(s_axi_wdata[65]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[193]),
        .O(m_axi_wdata[65]));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[66]_INST_0 
       (.I0(s_axi_wdata[66]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[194]),
        .O(m_axi_wdata[66]));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[67]_INST_0 
       (.I0(s_axi_wdata[67]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[195]),
        .O(m_axi_wdata[67]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[68]_INST_0 
       (.I0(s_axi_wdata[68]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[196]),
        .O(m_axi_wdata[68]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[69]_INST_0 
       (.I0(s_axi_wdata[69]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[197]),
        .O(m_axi_wdata[69]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[6]_INST_0 
       (.I0(s_axi_wdata[6]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[134]),
        .O(m_axi_wdata[6]));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[70]_INST_0 
       (.I0(s_axi_wdata[70]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[198]),
        .O(m_axi_wdata[70]));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[71]_INST_0 
       (.I0(s_axi_wdata[71]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[199]),
        .O(m_axi_wdata[71]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[72]_INST_0 
       (.I0(s_axi_wdata[72]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[200]),
        .O(m_axi_wdata[72]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[73]_INST_0 
       (.I0(s_axi_wdata[73]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[201]),
        .O(m_axi_wdata[73]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[74]_INST_0 
       (.I0(s_axi_wdata[74]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[202]),
        .O(m_axi_wdata[74]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[75]_INST_0 
       (.I0(s_axi_wdata[75]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[203]),
        .O(m_axi_wdata[75]));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[76]_INST_0 
       (.I0(s_axi_wdata[76]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[204]),
        .O(m_axi_wdata[76]));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[77]_INST_0 
       (.I0(s_axi_wdata[77]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[205]),
        .O(m_axi_wdata[77]));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[78]_INST_0 
       (.I0(s_axi_wdata[78]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[206]),
        .O(m_axi_wdata[78]));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[79]_INST_0 
       (.I0(s_axi_wdata[79]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[207]),
        .O(m_axi_wdata[79]));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[7]_INST_0 
       (.I0(s_axi_wdata[7]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[135]),
        .O(m_axi_wdata[7]));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[80]_INST_0 
       (.I0(s_axi_wdata[80]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[208]),
        .O(m_axi_wdata[80]));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[81]_INST_0 
       (.I0(s_axi_wdata[81]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[209]),
        .O(m_axi_wdata[81]));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[82]_INST_0 
       (.I0(s_axi_wdata[82]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[210]),
        .O(m_axi_wdata[82]));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[83]_INST_0 
       (.I0(s_axi_wdata[83]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[211]),
        .O(m_axi_wdata[83]));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[84]_INST_0 
       (.I0(s_axi_wdata[84]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[212]),
        .O(m_axi_wdata[84]));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[85]_INST_0 
       (.I0(s_axi_wdata[85]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[213]),
        .O(m_axi_wdata[85]));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[86]_INST_0 
       (.I0(s_axi_wdata[86]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[214]),
        .O(m_axi_wdata[86]));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[87]_INST_0 
       (.I0(s_axi_wdata[87]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[215]),
        .O(m_axi_wdata[87]));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[88]_INST_0 
       (.I0(s_axi_wdata[88]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[216]),
        .O(m_axi_wdata[88]));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[89]_INST_0 
       (.I0(s_axi_wdata[89]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[217]),
        .O(m_axi_wdata[89]));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[8]_INST_0 
       (.I0(s_axi_wdata[8]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[136]),
        .O(m_axi_wdata[8]));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[90]_INST_0 
       (.I0(s_axi_wdata[90]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[218]),
        .O(m_axi_wdata[90]));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[91]_INST_0 
       (.I0(s_axi_wdata[91]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[219]),
        .O(m_axi_wdata[91]));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[92]_INST_0 
       (.I0(s_axi_wdata[92]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[220]),
        .O(m_axi_wdata[92]));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[93]_INST_0 
       (.I0(s_axi_wdata[93]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[221]),
        .O(m_axi_wdata[93]));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[94]_INST_0 
       (.I0(s_axi_wdata[94]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[222]),
        .O(m_axi_wdata[94]));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[95]_INST_0 
       (.I0(s_axi_wdata[95]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[223]),
        .O(m_axi_wdata[95]));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[96]_INST_0 
       (.I0(s_axi_wdata[96]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[224]),
        .O(m_axi_wdata[96]));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[97]_INST_0 
       (.I0(s_axi_wdata[97]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[225]),
        .O(m_axi_wdata[97]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[98]_INST_0 
       (.I0(s_axi_wdata[98]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[226]),
        .O(m_axi_wdata[98]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[99]_INST_0 
       (.I0(s_axi_wdata[99]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[227]),
        .O(m_axi_wdata[99]));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wdata[9]_INST_0 
       (.I0(s_axi_wdata[9]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wdata[137]),
        .O(m_axi_wdata[9]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    m_axi_wlast_INST_0
       (.I0(\current_word_1_reg[1]_1 [6]),
        .I1(length_counter_1_reg[6]),
        .I2(m_axi_wlast_INST_0_i_1_n_0),
        .I3(length_counter_1_reg[7]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [7]),
        .O(\goreg_dm.dout_i_reg[9] ));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    m_axi_wlast_INST_0_i_1
       (.I0(\current_word_1_reg[1]_1 [4]),
        .I1(length_counter_1_reg[4]),
        .I2(m_axi_wlast_INST_0_i_2_n_0),
        .I3(length_counter_1_reg[5]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [5]),
        .O(m_axi_wlast_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    m_axi_wlast_INST_0_i_2
       (.I0(\current_word_1_reg[1]_1 [2]),
        .I1(length_counter_1_reg[2]),
        .I2(\length_counter_1[3]_i_2_n_0 ),
        .I3(length_counter_1_reg[3]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [3]),
        .O(m_axi_wlast_INST_0_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[0]_INST_0 
       (.I0(s_axi_wstrb[0]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[16]),
        .O(m_axi_wstrb[0]));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[10]_INST_0 
       (.I0(s_axi_wstrb[10]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[26]),
        .O(m_axi_wstrb[10]));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[11]_INST_0 
       (.I0(s_axi_wstrb[11]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[27]),
        .O(m_axi_wstrb[11]));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[12]_INST_0 
       (.I0(s_axi_wstrb[12]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[28]),
        .O(m_axi_wstrb[12]));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[13]_INST_0 
       (.I0(s_axi_wstrb[13]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[29]),
        .O(m_axi_wstrb[13]));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[14]_INST_0 
       (.I0(s_axi_wstrb[14]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[30]),
        .O(m_axi_wstrb[14]));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[15]_INST_0 
       (.I0(s_axi_wstrb[15]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[31]),
        .O(m_axi_wstrb[15]));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[1]_INST_0 
       (.I0(s_axi_wstrb[1]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[17]),
        .O(m_axi_wstrb[1]));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[2]_INST_0 
       (.I0(s_axi_wstrb[2]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[18]),
        .O(m_axi_wstrb[2]));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[3]_INST_0 
       (.I0(s_axi_wstrb[3]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[19]),
        .O(m_axi_wstrb[3]));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[4]_INST_0 
       (.I0(s_axi_wstrb[4]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[20]),
        .O(m_axi_wstrb[4]));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[5]_INST_0 
       (.I0(s_axi_wstrb[5]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[21]),
        .O(m_axi_wstrb[5]));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[6]_INST_0 
       (.I0(s_axi_wstrb[6]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[22]),
        .O(m_axi_wstrb[6]));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[7]_INST_0 
       (.I0(s_axi_wstrb[7]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[23]),
        .O(m_axi_wstrb[7]));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[8]_INST_0 
       (.I0(s_axi_wstrb[8]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[24]),
        .O(m_axi_wstrb[8]));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \m_axi_wstrb[9]_INST_0 
       (.I0(s_axi_wstrb[9]),
        .I1(\m_axi_wdata[127]_INST_0_i_1_n_0 ),
        .I2(s_axi_wstrb[25]),
        .O(m_axi_wstrb[9]));
endmodule

(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) 
(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) 
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
(* keep_hierarchy = "true" *) (* xpm_cdc = "ASYNC_RST" *) 
module axi4_dwtrans_xpm_cdc_async_rst
   (src_arst,
    dest_clk,
    dest_arst);
  input src_arst;
  input dest_clk;
  output dest_arst;

  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff;
  wire dest_clk;
  wire src_arst;

  assign dest_arst = arststages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(1'b0),
        .PRE(src_arst),
        .Q(arststages_ff[0]));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(arststages_ff[0]),
        .PRE(src_arst),
        .Q(arststages_ff[1]));
endmodule

(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) 
(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) 
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
(* keep_hierarchy = "true" *) (* xpm_cdc = "ASYNC_RST" *) 
module axi4_dwtrans_xpm_cdc_async_rst__3
   (src_arst,
    dest_clk,
    dest_arst);
  input src_arst;
  input dest_clk;
  output dest_arst;

  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff;
  wire dest_clk;
  wire src_arst;

  assign dest_arst = arststages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(1'b0),
        .PRE(src_arst),
        .Q(arststages_ff[0]));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(arststages_ff[0]),
        .PRE(src_arst),
        .Q(arststages_ff[1]));
endmodule

(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) 
(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) 
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
(* keep_hierarchy = "true" *) (* xpm_cdc = "ASYNC_RST" *) 
module axi4_dwtrans_xpm_cdc_async_rst__4
   (src_arst,
    dest_clk,
    dest_arst);
  input src_arst;
  input dest_clk;
  output dest_arst;

  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff;
  wire dest_clk;
  wire src_arst;

  assign dest_arst = arststages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(1'b0),
        .PRE(src_arst),
        .Q(arststages_ff[0]));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(arststages_ff[0]),
        .PRE(src_arst),
        .Q(arststages_ff[1]));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2022.2"
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2021_07", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`pragma protect key_block
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`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 241936)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
